Can I find some documentation/details on how the Out-Of-Order works and what
are the micro architectural features it supports ? ( other than just looking at
source-code )
I suppose more folks are using Flexus for multicore/multiprocessor simulations
and not interested in the uArch, but :
- is there any branch prediction modeled ?
- register renaming ?
- detailed timing of Execution units ( for example ADD 1 cycle, MULT 10
cycles, FPDIV 1000 cycles , etc ) or multiple execution units ?
I can not find those uArch parameters on a quick look. Maybe I am not looking
in the right place, or they were not even there in the first place. If so, is
anyone working on that or who has more detailed simulator models ?
Eugen
