Dear Eugen,

Unfortunately, there is no document that describes the details of OoO and 
microarchitectural features you are interested in. However, the Flexus code has 
very good comments and I am sure you can find all the details easily from the 
source code.

To answer your second question, I have to say that there is a Tournament branch 
predictor implemented in Flexus.  This branch predictor chooses between a 
gShare and Bimodal branch predictors. You can find the details at 
FLEXUS_PATH/components/Common/BranchPredictor.[cpp or hpp].

Also, register renaming process is implemented in Flexus. You can find the 
details at FLEXUS_PATH/components/uArch
/MapTable.hpp
. It is remarkable that this is a high level register renaming implementation. 
This means that it does not model all the details of register renaming at RTL.

In Flexus, the latency of all execution units (add, sub, mult, div, etc.) is 1. 
This means that if all operands of an operation are ready, the operation will 
be performed in 1 clock cycles.

________________________________________
From: simflex-bounces at ece.cmu.edu [simflex-bounces at ece.cmu.edu] On Behalf 
Of Leontie Eugen [e_leontie at yahoo.com]
Sent: Thursday, July 09, 2009 11:21 PM
To: simflex at ece.cmu.edu
Subject: [Simflex] OutofOrder in detail

Can I find some documentation/details on how the Out-Of-Order works and what 
are the micro architectural features it supports ? ( other than just looking at 
source-code )

I suppose more folks are using Flexus for multicore/multiprocessor simulations 
and not interested in the uArch, but :
 - is there any branch prediction modeled ?
 - register renaming ?
 - detailed timing of Execution units ( for example ADD 1 cycle, MULT 10 
cycles, FPDIV 1000 cycles , etc ) or multiple execution units ?

I can not find those uArch parameters on a quick look. Maybe I am not looking 
in the right place, or they were not even there in the first place. If so, is 
anyone working on that or who has more detailed simulator models ?

Eugen



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