> On May 18, 2017, at 3:26 AM, Johnny Billquist <[email protected]> wrote:
>
> On 2017-05-18 03:23, Paul Koning wrote:
>> ...
>
>> Is MT_ASTLVL defined as a register where only the low byte has meaning?
>
> Seems like it was using even fewer than 8 bits... Looked like it was only 3
> bits. But the register itself seems to be defined as 32 bits. I'm not even
> sure any processor internal registers can be anything else.
>
> All that said, Matt Burke seems like he already identified the issue pretty
> correctly. The VAX 11/780 Hardware Handbook seems to clearly say that bit
> 3-31 are ignored, and returns as 0 on read. So for that model, I guess the
> value should be masked.
>
> However, this might be different on different CPU models, so I suspect this
> should be applied with care. He was testing VAX/VMS V4.5, which is pretty
> ancient. The models supported by that version would probably only be the
> VAX-11 models. (And yes, I include the 86x0 in the VAX-11 series.)
The VAX architecture reference manual shows that register the same way (3 LSB
are meaningful, rest is ignored on write, read as zero). So that seems to say
this is a standard definition, not a model-specific one, and it is safe for
software not to worry about those other bits when writing the register.
paul
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