This is a test that tests something which is actually implementation
dependent. So you need to run the appropriate test on the appropriate CPU.
More specifically:
The following processor uses the original content of Rn as source when
doing an operation like MOV Rn,(Rn)+
LSI-11, 11/04, 11/05, 11/10, 11/34, 11/44, 11/45, 11/70.
The following processors uses the modified content of Rn as source when
doing an operation like MOV Rn,(Rn)+
11/15, 11/20, 11/23, 11/24, 11/35, 11/40, 11/60, J11
So, depending on which CPU you are planning to emulate, you need to do
this differently...
And just so you know, there are other implementation defined differences
between different models as well, which you probably should research, if
you want your emulation to behave correctly...
Johnny
On 2020-07-10 00:00, Paul Moore wrote:
Not sure if you are interested but I found that simh fails test 14.
(Running the tests on my own emu project and wondered if simh would pass
all of these nasty tests too)
007176: 010700 mov
r7,r0 ; @.
007200: 012700 006340 mov
#6340,r0 ; @.`.
007204: 010020 mov
r0,(r0)+ ; ..
007206: 026727 177126 006342 cmp
6340,#6342 ; W-V~b.
007214: 001401 beq
7220 ; ..
007216: 000000
halt ; ..
If you don’t know these test the general layout is as follows
Load pc in r0 (presumably to identify the test if a halt occurs)
Run the test
Halt if fail
Next test
Simh halts at 7220
This test is verifying the behavior of using the contents of an auto
increment register. IE exactly when does the register change value in
the instruction flow
Mov r0,(r0)+
Their test expects the value moved to DD to be the new value of R0. Ie
the incremented register value is committed as soon as it is used to
calculate the address
Simh(v4) (running as 11/05 not tried other models) moves the old value.
Ie the register update is not processed until the instruction is complete
sim> e r0
R0: 006342
sim> e 6340
6340: 006340
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