Predicting the spurious frequencies generated by a DDS can be a challenge,
but is possible.   Take the clock frequency and the fundamental generated.
Then calculate the harmonics of the fundamental up to quite a high order,
and then calculate what the alliassed result is of these for the harmonics
of the clock.

You need to calculate all the values of    Fspur = N.Fclock +/- M.Fgen  up
to a surprisingly high set of values for N and M - just he job for a
spreadsheet or VB programming exercise!    The chances are that one product,
somewhere, will come out unpleasently close to the wanted output, and it is
quite illuminating to see just how quickly the spurii change for even a
modest shift in output frequency.

More seriously, it does allow you to see the amount of cleaning up that will
be required, and work out what sort of PLL will have to be built.

Also,  Not  directly applicable to this reflector, but of value hopefully...

I have several times used a DDS to phase lock the source for microwave
beacons.  Here, the DDS is cleaned up in a PLL using a series resonant
crystal running at around 100MHz which is them multiplied up to the
microwave frequency.   The crystal is operatd as a VCXO by adding a varicap
in series with it - this usually results in a VCO constant somewhere between
80 - 200Hz / volt (at 100MHz).   I need to phase lock the crystal source to
a GPS DO supplying 10MHz, so the DDS is operated 'in reverse', being clocked
by the VCXO and generating 10MHz which goes off to the phase comparator and
PLL filter.

Since the comparison frequency is at 10MHz, a very simple PLL becomes
possible - I use an exclusive or gate and the simplest C-R filter.  The aim
is to get as WIDE a loop bandwidth as possible to allow freqeuncy shift
keying to be generated by re-programming the DDS.  With the loop as
described, there is no troubnle getting 850Hz shift RTTY at 10GHz (RF
multiplication of *96).  The bandwidth of the PLL is dictated by the product
of VCO constant and Phase Detector, so can never be wider than a couple of
hundred Hz, more than enough to clean up the DDS, so no real need for any
loop filtering other than to remove the 10MHz comparison frequency
component.

Details of the phase locking for GB3SCX on 10GHz and GB3SCK on 3.4GHz can be
found at www.scrbg.org/g4jnt/

Andy  G4JNT


-----Original Message-----
From: dcappels <[EMAIL PROTECTED]>
To: [email protected] <[email protected]>
Date: 2006/01/26 15:17
Subject: [soft_radio] Re: DDS + PLL to clean up spurs?


>Yes, this is probably the best solution. You would count on the loop
>filter (no pun intended) to take out most of the spurs. Also, some
>have noted that some buffering is required between the VCO and the
>counter to keep noise from the counter chain from getting into the VCO.
>
>--- In [email protected], "sis108" <[EMAIL PROTECTED]> wrote:
>>
>> I often wondered why you couldn't use a 1x VCO and phase detctor.
>>
>> IE DDS 50-60Mhz out VCO 50-60MHZ both phase detectors 50-60mhz in.
>> Hopefully the loop filter would kill the spurs.
>>
>> I have not found high speed phase/freq detectors however.
>>
>> Anyone have an opinion on how well this might work to kill the spurs?
>>
>>
>> --- In [email protected], KY1K <[EMAIL PROTECTED]> wrote:
>> >
>> > Has any amateur ever done a DDS in conjunction with a PLL to clean up
>> > spurs? I hear chatter about it working well if the PLL is designed
>> > properly, but have never run across any real life examples of the 2
>> > technologies rolled into one.
>> >
>> > I understand the DDS has advantages, especially in it's ability to
>> > change frequency quickly. But, if rapid qsy's are not needed, I would
>> > think a PLL with a slow response time in the filter would be as good
>> > or better with respect to spectral purity than any DDS available
>today.
>> >
>> > Appreciate any pointers to web resources discussing this topic.
>> >
>> > Thanks,
>> >
>> >
>> > Art
>> >
>>
>
>
>
>
>
>
>
>Yahoo! Groups Links
>
>
>
>
>
>



 
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