DDS Notes from Chp. 16, ARRL HB 2005 Summary of this will show that the DDS is a polluted method of signal generation!
It might be interesting but it surely is not efficient. Too many processes and things to over come here! So argue amongst yourselves. As you read this, count all of the problems and technical difficulties this method is plagued with! Then vote! Note that there is no such thing in this article as good DDS phase noise characteristics! Very little appears to be good once you begin reading this! "A DDS system generates digital samples of a sine wave and converts them to an analog signal using a DAC. In a DDS chip, a phase accumulator is incremented at each clock time; the phase information is used to look up a sine-wave amplitude from a table. This value is passed to the DAC, which outputs a step-wise sine wave. *As we saw before, the spectrum of this sine wave is seasoned with aliases and contains other minor pollutants. Since the phase is represented by a binary number with a fixed number of bits, p, *errors develop because the number is truncated to that number of bits. Truncation generates PM spurs in the DDS output. This occurs prior to the DAC. Further errors are related to the output resolution of the look-up table. Table values representing the amplitudes are truncated to some number of bits, a. *This mechanism produces AM spurs in the output. *Phase noise at the output is that of the DDS clock source times the ratio of the output frequency to the clock frequency, as limited by divider noise. *Spurious levels also tend to grow as the DDS output frequency approaches the Nyquist limit. Strange spurs at the output are usually related to IMD and harmonics of the desired signal and their aliases. Remember that frequencies exceeding half the sampling frequency fold back into the signal spectrum at a position determined by their frequency, modulo fs/2. High-order harmonics are liable to find their way into ones band of interest. *Traps at the DAC output have been known to suppress these responses. See Project F in the Appendix for the schematic of a DDS project. In the analog signal we generate, *the DAC introduces more AM spurs, harmonics and IMD because of its inherent nonlinearity, as discussed above. *Spurs are also likely at the clock frequency, its harmonics and sub-harmonics. A higherorder LPF will take care of these, but we must see what we can do about the others. It turns out we may eliminate all the AM spurs by squaring the DDS output. *We can do nothing about the remaining PM spurs. Cranking through Eq 28 will show that they can be made very low: 113 dBc for a 20-bit-address sine look-up table and 32-bit phase accumulator. This parameter is critical in case we want to use the DDS as the reference to a high-frequency PLL circuit. *The PLL will multiply the phase noise and PM spurs by the ratio of the PLL output frequency to the PLL reference frequency within the PLL loop BW. Outside the loop BW, the VCO itself is responsible for establishing spectral purity. *So while dividing the DDS to the PLL reference frequency lowers phase noise and PM spurs, the PLL multiplies them back upward. A trade-off exists between spur levels and reference frequency, hence lock time. A PLL reference frequency near 100 kHz has been found to be sufficient for the desired lock times, with an output-toreference ratio of 1000. Such a loop should achieve very fast lock times, as it can be expected to lock within 500 cycles of the reference input. The DDS tuning time is at least three orders of magnitude faster than this. In the example, the VCO output is near 100 MHz. DDS energy is injected at the reference input to the PLL chip, squaring it and dividing it by 10; the DDS runs near 1000 kHz. The block diagram of a PLL using a DDS as its reference is shown in Fig 16.20. Spurs and phase noise inside a loop BW of, say, 1 kHz are amplified by the PLL by the factor: dB 40 f f log 20 N REF VCO = ? ? ? ? ? ?? ? = (30) Of course, we tune the hybrid synthesizer by programming the DDS; the PLL programming is fixed. Lets say we want 1-Hz tuning resolution at the VCO output. As the DDS frequency is 1/100 of the output, we must tune the DDS in 10 millihertz steps! Tuning resolution in a DDS circuit is determined by the phase accumulators bit resolution, p, and the DDS clocks frequency, fclk: p clk DDS 2 f df = (31) A clock frequency around 10 MHz and p = 32 easily satisfy our conditions, producing a step size of 2.3 millihertz. As noted above, making the DDS output frequency a small fraction of the clock frequency makes it easier to get a clean output. A range of about half an octave eases the design of the LPF or BPF used at the DDS output to limit spurs, aliases and clock feed-through. The phase-accumulator/look-up-table approach is equally useful in generating numeric BFOs in software. One of the first things to emerge when considering this scheme is the potentially large size of the look-up table. To maintain the full dynamic range of a DSP system requires BFO phase and amplitude performance, as limited by Eqs 28 and 29, at least as good as the rest of the system. In 16-bit systems, we are shooting for about 90- 100 dB of dynamic range. A table with 216 = 65,536 entries is not much of a problem for DDS chip manufacturers to include onboard, but it may tax available memory space in embedded systems. Fortunately, a couple of ways around the problem have been uncovered. The first involves the process of interpolation, very much like the artificial increase of sampling frequencies we examined above. In this method, we restrict the number of table entries to some arbitrary number, M << 216, while keeping the bit-resolution of the entries themselves, a, high enough to satisfy the limits of Eq 29 for the spur levels we can tolerate. Take the case where ? = 28 = 256 and a = 16. The phase accumulator, incremented at each sample time by an amount df that is directly proportional to the output frequency, forms the address into the look-up table. Let this address have bit-resolution p = 16. According to Eq 28, PM spurs will not exceed 91 dBc. Since there are only 256 table entries, we may use the most-significant byte (MSB) of the address to find the table entries that straddle the correct output value. We then use the least-significant byte (LSB) as an unsigned fraction to find out how far between the two table entries we must go to reach the correct output value. If, in order of increasing address in the table, our two adjacent table entries are d1 and d2, we may perform a first-order interpolation between the entries using: etc..." _____________________________________________________________________ Call Anyone, Anytime, Anywhere in the World - FREE! Free Internet calling from NetZero Voice Visit http://www.netzerovoice.com today! ------------------------ Yahoo! Groups Sponsor --------------------~--> You can search right from your browser? It's easy and it's free. See how. http://us.click.yahoo.com/_7bhrC/NGxNAA/yQLSAA/ELTolB/TM --------------------------------------------------------------------~-> Yahoo! Groups Links <*> To visit your group on the web, go to: http://groups.yahoo.com/group/soft_radio/ <*> To unsubscribe from this group, send an email to: [EMAIL PROTECTED] <*> Your use of Yahoo! Groups is subject to: http://docs.yahoo.com/info/terms/
