Referring to the Triggered H&P circuit diagram I have uploaded into
the soft_radio group files section. Which is on the first file page
and not in a folder; as a PDF file.
http://groups.yahoo.com/group/soft_radio/files/Triggered%20H%26P%20by%20Daniel%20Jackson%20ka9rza.pdf
If interested, keep a copy of this post in your files to consult in
regard to the circuit diagram.
To date, the Huff & Puff VFO Stabilizer has seen allot of the use of
the 74HC74 Dual D Flip Flop IC by builders in the making of the
circuit. However this IC has only been used as a basic source to
create a quick oscillator and or as a quickly thrown together mixer
for edge triggered comparison.
Actually each flip flop section in the IC has 4 inputs and 2
outputs. And actual trigger functions exist in the IC although to
date the H&P designs have not been using the IC correctly in its pin
out logic. Altogether there are 8 inputs and 4 outputs once you
understand the IC correctly. Likewise the H&P experimenters only seem
to use 1/2 of the IC. The inputs are D, >CLK, /CLR, /PRE. The outputs
are Q, and /Q. And there are thus two separate flip flops so there
are double this many inputs and outputs.
Once it is understood that the economy of extra inputs and mixing as
well as triggering features are incorporated onto this one IC, a
redesign of the Huff & Puff with a new standardized heart with more
functions and features has resulted from my test here on the work
bench. And how this escaped former builders I do not know. But it
does work better. It is more of a reliable circuit to get up and
running.
I tested my circuit diagram today by making gross adjustments to the
resistors in the actual test model to see if the circuit still worked
somewhat afterwards; for and idea of circuit repeatability. The
results where that the circuit still worked when I changed the 1K
resistor to 10K, 100K and then to 1M. Regardless, it still worked.
Hence it should be very repeatable.
Note: in the circuit you must keep the oscillator coil's reactance
XL around 500 to 1000 ohms to keep the Q high in the region you design
the VFO for HF operation in, or the 74HC4060 will not oscillate!
Now that there is a more advanced way to make the most of this one
IC in the H&P Stabilizer, the other ideas that were figured on being
tried by former builders can be added after this stage. I am sure
that once every H&P builder revisits the H&P with my new circuit
design that they will agree this approach of operation is much better
and should be left as it is as the basis and foundation of a new
circuit architecture. Adding the other matters in the design that one
may desire after this new circuit. So there is a defined heart to the
circuit now. One that is more advanced in concepts making the most of
the 74HC74 using concepts of trigger, sample and hold. Where there is
a central time base reference, a sample and a lower sample that acts
as the trigger and reset mechanism of the compared sample. Using
binary bit information and digital logic to achieve a better result.
Yes it is purely digital now! And I have more circuit features coming
that I have already up and running here in testing, to make more use
of the other half of the 74HC74.
If you wish to use this particular H&P circuit in the way that a PLL
circuit is used, by dividing down the VCO frequency to lower it and
make its tuning more incremental than do so by taking your output off
of PIN 7 on the 74HC4060 which is a division by 16 binary bit and
hence is digital at this point. PIN 7 is also used in my circuit by
the 74HC74. The phase noise and stepping corrections will be way
lower than the PLL by comparison. I can tell you this, DDS can not
compete with these sort of technical specifications. The lock step
correction of the H&P is +/- 1 Hz and I have seen it for myself here
with my equipment. This is more than ideal for SDR where low phase
noise and extremely stable frequencies are required. And please
experiment and learn all you can about it. This circuit should work
for you in the regions I have it running and you should be able to
scale it for your range of frequencies if you are resonable on your
tuned circuit reactances for your desired region of operation.
If you use it on its fundamental frequency without binary division,
then you have a lock thats accurate in step to +/- 1 Hz for the most
part, and thats extremely more accurate than you need, only 1 Hz
stepping and phase noise on average due to the sample and hold
circuitry. The lock however occurs in different places in each 1Khz
segment tuned into. So use a crystal mixer to convert the VFO
frequency to some other receiver heterodyne frequency and then add
incremental tuning to the mixer crystal with a small variable
capacitor so you can cover any frequency down to 1 Hz tuning by
placing the incremental tuning in the crystal controlled mixer
section. Anyways you will have a VFO for general coverage use and
some extreme frequency control and tuning ability if you follow this
scheme. The crystal should be able to be tuned back and forth +/-
3Khz for good measure.
Now the VFO will have such other things as ripple and some phase
noise it produces in the VFO section. These however are being
controlled by the H&P circuit to reduce them down below the common un
controlled VFO in comparison. And if you are still too much of a
stickler for performance, then just divide it down as the typical PLL
circuit does and then use that and have some below 1 Hz noise and
stepping corrections. In other words; accuracies in tenths of a hertz
scale!
Dan ka9rza
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