{Huff Puff VFO With SDR!}
The economics of the design! 455 KHz and 10.7 Mhz i.f.
sections.http://bojangles984.pbwiki.com/f/Push%20Pull%20VFO%20Sychronizer.zip
Some pointers for using the "Push Pull VFO Synchronizer" is to
increase the "metal enclosed oscillator" frequency up into the 40 Mhz
and above regions for better comparison of the 455~1455 kHz VFO. The
higher the oscillator the better; as I said earlier on, it works
better with my 36 MHz oscillator than the 24 MHz version. Max
frequency input to the 74HC74 is rated at 82 MHz when Vcc is 6 volts.
At 5 volts the frequency will be above the 4 volt frequency of 69 MHz
and below 82 MHz. According to the technical data sheets. So
eventually we will use the highest frequency oscillator we can find to
get better performance if possible.
Also these circuits do not have to have any specialized support
circuitry such as i.f. transformers between ICs to match sections.
The TTL output level time base will wire its input directly into D of
the 74HC74 without any transformers.
The idea of using a low VFO frequency range (455~1455 kHz) for better
stability due to low operating frequency and a contrasting, high MHz,
HF time base clock oscillator for the comparator time reference; fits
in with economy as well as a better scheme which draws upon the 10.7
Mhz and 455 KHz i.f. receiver schemes. Economy meaning that medium
wave broadcast type main tuning variable capacitors can be used for
the VFO itself and that commonly available CB Radio PLL crystals of
the 10.240 MHz type can be used to mix the VFO up to 10.7 MHz. The
device then can be used with a QSD circuit to sample the i.f. channels
of receivers both of the 455 kHz type and the 10.7 MHz type. The same
10.240 MHz/VFO mixer oscillator section can also supply a 10.240 MHz
signal to another mixer to convert a 455 KHz incoming i.f. to 10.7 MHz
and then to a single 10.7 Mhz range QSD circuit for use with SDR. So
this defines the economy of the overall scheme. The end result is
that a 10.7 MHz i.f. will always go directly to the 10.7 MHz QSD
circuit and that a 455 kHz i.f. is up converted to 10.7 MHz then goes
to the 10.7 MHz QSD circuit. And all of this from one economic to
produce model.
If a good broadcast variable capacitor cost around $7 then the
entire circuit can be built for around $14 with good shopping. A
printed circuit board will raise the price somewhat also.
The circuit uses a charge pump idea similar to the PLL circuits and
this is in the two 100uF capacitors on the diode voltage control loop.
These store up a charge from the two control signal inputs from the
transistor Q1 and the Q output of the 74HC74. It might seem that they
will completely destroy any a.c. signal, being they are somewhat large
in capacitance but they do not prevent a contol signal from reaching
the diodes in regard to a high speed correction pulse: I can see this
on my oscilloscope. These capacitors sort of normalize the signal
voltage to the diode and also divide the 5 volt supply voltage into
two for a sort of voltage divider bias that runs mid way between 0 and
5 volts. Removal of these capacitors results in the raw a.c. signal
voltage reaching the Varicap diode in a large magnitude and the VFO
then goes wild.
There remains this matter of the time constant of the diode loop
circuit and that is yet to be explored and wide open for examination
if someone wishes to look at it. I feel that getting the time
constant right might result in even better performance.
The outputs of the 74HC4060 in this model are low enough in
frequency (after internal binary division) that you can actually use a
software based oscilloscope meant for audio to look at them if the
software reads up into the 100 Khz range. Of course you will not have
a good trigger and hold, at least I don't think so. I would have to
look at some of my oscilloscope softwares to see if they have a good
synchronous triggering feature?
In after a year or so once the right kind of folk with diverse kinds
of views have experimented with this circuit, and there is a
compilation of ideas and views along with improvements brought
together; then we can have something hopefully more ideal in terms of
this circuit to suit SDR. I am sure that the circuit is worth more
research and innovation for these goals of SDR usage.
Those of you who finds these threads in the future or who come back
to them and have some questions or input on your findings and perhaps
innovation to this circuit concept can email me ka9rza at
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