On 14 Mar 2007 at 9:10, D. J. Wang wrote: > Hi Janne, > To avoid the spurs from DDS altogether it may be easier to use a PLL/VCO > instead. I was planning to build a 400-900 MHz PLL to drive the SDR hardware > but I don't have time to do it. Freq resolution of this PLL doesn't need to > be high since Winrad can cover a 48-192KHz window. PLL step size can be in > the range of 200KHz. It may be easier to build than the DDS. Minicircuit > Labs' POS-900W VCO will be a good choice for this. I am not sure whether you > can find a 7474 type of flipflop fast enough to cover the freq range you need > as it need to be able to divide >200MHz clock. > > 73 de DJ/NM3R > A 74AUC74 toggles at 350 MHz minimum at Vcc = 2.5V. Unfortunately, it is only available in a QFN package, so a PCB is a must.
Dave - WB6DHW <http://users.wildblue.net/wb6dhw>
