Pi filter power supply values and how it relates to filtering the power lines on the QSD.
Hello, I was doing some testing and reading on power supply filtering. I found an interesting article at www.designers-guide.org/Design/bypassing.pdf talking about decoupling, bypassing and also how to select and place the L C R components in low pass filters. I would like your best empirical suggestions on good power filtering circuits. I guess that my questions is that how do I choose the values of a pi network (or an LC network) to make good supply filtering. Let me tell you about my analysis development and how I seem to be hitting some stumbling blocks. I put an LC low pass filter made up of a inductor and two parallel capacitors: one Aluminum and one x7r surface mount capacitor. I used this to regulate the Vcc line of the digital ICs attacking the QSD multiplexer network. My overall goal with that was to keep the output of a 7805 regulator as stable as possible in voltage, so I thought the first step would be to get rid of current impulse spikes caused by the digital circuits. I would expect the voltage regulator to get a high isolation from the load considering that the inductor is good at keeping the current going through it as a continuous function of time. The voltage is allowed to be discontinuous, with abrupt changes, governed by V = L di/dt. I originally modeled the load attached to the LC network as a pure resistor, knowing that it was much simpler that the digital IC load. A better model would be a periodic impulse current source, sinking current from the LC network. I was hoping that the digital IC will be taking the current from the capacitor such that the di/dt on the inductor would be zero. Current spikes have a huge di/dt, so the catch would be to make a good passive component set value selection. I used the second order differential equation for the RLC as a starting point for the values. I checked up the location of the poles with the inductor parasitic resistance and made for sure I got real valued poles. I used a pretty big inductor to be sure to dominate over the parasitic inductor in the Al capacitor. Of course, I made the cutoff frequency several decades away the quadruple carrier switching frequency of a QSD. So I powered up the circuit and saw a periodic voltage fluctuation at the digital IC Vcc line. On the output of the NAND gate that is attacking my SQD switch IC, I get http://i17.tinypic.com/62dgile.jpg. The Vcc line looks exactly like the non- zero portion of the graph, i.e. the camel hump reproduced for all time. The current on the capacitor is i = c dv/dt. If I pull current any current at all from a capacitor that means that dv/dt can't be zero. One must admit that the voltage relation on the capacitor is more friendly than the one for the inductor, being v= 1/c int( i(t)). Here, the capacitor voltage is exactly the Vcc voltage of the digital logic. So the problem looks fundamental. I am also suspecting that the idea of using real poles as a goal in the R L C circuit is flawed. For the moment I think that I only get good isolation. I could probably just put a tiny resistor in series with the inductor and check if the current flowing through it is constant. So, if you have successfully used pi networks, how do would you recommend them to be designed? Frank
