Ah. I've got it now, I think. You would do what the SoftRock does in the FPGA. That's almost too easy.
I'm still a little confused about sampled bandwidth and center frequency. Is the center frequency simply half the sampling frequency, and the quadrature clock 2x the sampling frequency (or 4x the center frequency)? When Leon mentioned undersampling, is that just anti-aliasing with a BPF in front of the A/D? And beyond 600 MHz, the sine series coefficient is too large, and the losses too great? ----- Original Message ----- From: k5nwa To: [email protected] Sent: Wednesday, April 30, 2008 3:49 PM Subject: Re: [softrock40] Standalone SoftRock. Q's about Xilinx DSP FPGA At 12:25 PM 4/30/2008, you wrote: How would that work? For the 100 MHz sampling A/D, would you sample at baseband, and then run 2x 50 million point FFTs, 10 times or more per second? Can the Spartan-3 DSP do that? That is not how you would do it, unless you are a glutton for punishment, or that was a requirement. You first cut down the data rate as follows, although there are a variety of ways in doing it; 1. You use a digital half mixer to bring the spectrum you want down to the base band. Let's say you are interested in the 40M band you mix the incoming signals with a 7.1MHz LO that is digitally generated. 2. You filter the signal with a low pass filter so a smaller amount of the frequencies is available now instead of 10's of MHz you have a more narrow range but remember that you are only interested in the sample around frequency 0. 3. You decimate, that is you throw away all but 1 in N samples, if N is 4 you take one reading and throw away 3, then you repeat that pattern, now you data rate is 1/N of what it used to be. 4. Repeat steps 2 and 3 until you get to a rate that you want such as 192KHz of data left. You repeat it in sections because it's more efficient for N to be a small number What you end up with is a 192KHz band centered around 7.1MHz, now you proceed to do the other process such as FFT for your display, to demodulate you repeat the steps 1 to 4 to bring a chunk of the 192 KHz down to lets say a 8KHz rate to demodulate and filter a SSB signal. And here is the part that many people find hard to believe, it your fast A/D was a 16 bit A/D the data you end up with may be 20+ bits in resolution and dynamic range, the reason is when you decimate you actually increase the accuracy of the output. if you had four reading saying 10, 11,10,10, into the the filter the output of decimation is 10.25 which is a more accurate representation of what happened during those 4 readings Steps one through four bring down the data rate to a level that the FFT can more easily deal with rather than some ridiculous rate like 66MHz that you started out with, still you would be surprised as to how much faster a FPGA is compared to a CPU, it does multiple things at once not in a serial fashion unless you choose to do so, so it's way faster. The FPGA in that demo board could process live video signals and have not problems. How fast it performs is determined by how much hardware you dedicate to the task and how many task you do simultaneously. I consider myself a rookie when it comes to Verilog, but I intend to work on it in the future. Cecil K5NWA www.softrockradio.org www.qrpradio.com "Blessed are the cracked, for they shall let in the light."
