----- Original Message ----- From: Mike Young To: [email protected] Sent: Thursday, May 01, 2008 12:12 AM Subject: Re: [softrock40] Standalone SoftRock. Q's about Xilinx DSP FPGA
Ah. I've got it now, I think. You would do what the SoftRock does in the FPGA. That's almost too easy. I'm still a little confused about sampled bandwidth and center frequency. Is the center frequency simply half the sampling frequency, and the quadrature clock 2x the sampling frequency (or 4x the center frequency)? When Leon mentioned undersampling, is that just anti-aliasing with a BPF in front of the A/D? And beyond 600 MHz, the sine series coefficient is too large, and the losses too great? Here's an explanation: http://www.national.com/appinfo/adc/files/Undersampling.pdf Leon -- Leon Heller Amateur radio call-sign G1HSM Yaesu FT-817ND transceiver Suzuki SV1000S motorcycle [EMAIL PROTECTED] http://www.geocities.com/leon_heller
