Module Name:    src
Committed By:   martin
Date:           Sun Sep  1 10:19:04 UTC 2019

Modified Files:
        src/sys/dev/mii [netbsd-8]: ciphy.c ciphyreg.h

Log Message:
Pull up the following revisions, requested by msaitoh in ticket #1350:

        sys/dev/mii/ciphy.c                             1.27-1.28, 1.30, 1.32
                                                        via patch
        sys/dev/mii/ciphyreg.h                          1.6

- The register bit definitions from register 0 to 15 in ciphyreg.h
  conform to the 802.3 spec, so remove them and use mii.h's definition.
  No functional change.
- Add CS8204, CS8244 VSC8211 and VSC8601 support from {Free,Open}BSD.
- KNF.


To generate a diff of this commit:
cvs rdiff -u -r1.26.10.1 -r1.26.10.2 src/sys/dev/mii/ciphy.c
cvs rdiff -u -r1.5 -r1.5.20.1 src/sys/dev/mii/ciphyreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/dev/mii/ciphy.c
diff -u src/sys/dev/mii/ciphy.c:1.26.10.1 src/sys/dev/mii/ciphy.c:1.26.10.2
--- src/sys/dev/mii/ciphy.c:1.26.10.1	Mon May 13 12:40:13 2019
+++ src/sys/dev/mii/ciphy.c	Sun Sep  1 10:19:04 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: ciphy.c,v 1.26.10.1 2019/05/13 12:40:13 martin Exp $ */
+/* $NetBSD: ciphy.c,v 1.26.10.2 2019/09/01 10:19:04 martin Exp $ */
 
 /*-
  * Copyright (c) 2004
@@ -35,7 +35,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ciphy.c,v 1.26.10.1 2019/05/13 12:40:13 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ciphy.c,v 1.26.10.2 2019/09/01 10:19:04 martin Exp $");
 
 /*
  * Driver for the Cicada CS8201 10/100/1000 copper PHY.
@@ -83,6 +83,15 @@ static const struct mii_phydesc ciphys[]
 	{ MII_OUI_CICADA,		MII_MODEL_CICADA_CS8201B,
 	  MII_STR_CICADA_CS8201B },
 
+	{ MII_OUI_CICADA,		MII_MODEL_CICADA_CS8204,
+	  MII_STR_CICADA_CS8204 },
+
+	{ MII_OUI_CICADA,		MII_MODEL_CICADA_VSC8211,
+	  MII_STR_CICADA_VSC8211 },
+
+	{ MII_OUI_CICADA,		MII_MODEL_CICADA_CS8244,
+	  MII_STR_CICADA_CS8244 },
+
 	{ MII_OUI_xxCICADA,		MII_MODEL_CICADA_CS8201,
 	  MII_STR_CICADA_CS8201 },
 
@@ -92,6 +101,9 @@ static const struct mii_phydesc ciphys[]
 	{ MII_OUI_xxCICADA,		MII_MODEL_xxCICADA_CS8201B,
 	  MII_STR_xxCICADA_CS8201B },
 
+	{ MII_OUI_VITESSE,		MII_MODEL_VITESSE_VSC8601,
+	  MII_STR_VITESSE_VSC8601 },
+
 	{ 0,				0,
 	  NULL },
 };
@@ -103,9 +115,9 @@ ciphymatch(device_t parent, cfdata_t mat
 	struct mii_attach_args *ma = aux;
 
 	if (mii_phy_match(ma, ciphys) != NULL)
-		return (10);
+		return 10;
 
-	return (0);
+	return 0;
 }
 
 static void
@@ -151,11 +163,9 @@ ciphy_service(struct mii_softc *sc, stru
 
 	switch (cmd) {
 	case MII_POLLSTAT:
-		/*
-		 * If we're not polling our PHY instance, just return.
-		 */
+		/* If we're not polling our PHY instance, just return. */
 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
-			return (0);
+			return 0;
 		break;
 
 	case MII_MEDIACHG:
@@ -166,12 +176,10 @@ ciphy_service(struct mii_softc *sc, stru
 		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
 			reg = PHY_READ(sc, MII_BMCR);
 			PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
-			return (0);
+			return 0;
 		}
 
-		/*
-		 * If the interface is not up, don't do anything.
-		 */
+		/* If the interface is not up, don't do anything. */
 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 			break;
 
@@ -180,40 +188,37 @@ ciphy_service(struct mii_softc *sc, stru
 		switch (IFM_SUBTYPE(ife->ifm_media)) {
 		case IFM_AUTO:
 #ifdef foo
-			/*
-			 * If we're already in auto mode, just return.
-			 */
-			if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
-				return (0);
+			/* If we're already in auto mode, just return. */
+			if (PHY_READ(sc, MII_BMCR) & BMCR_AUTOEN)
+				return 0;
 #endif
 			(void) mii_phy_auto(sc, 0);
 			break;
 		case IFM_1000_T:
-			speed = CIPHY_S1000;
+			speed = BMCR_S1000;
 			goto setit;
 		case IFM_100_TX:
-			speed = CIPHY_S100;
+			speed = BMCR_S100;
 			goto setit;
 		case IFM_10_T:
-			speed = CIPHY_S10;
+			speed = BMCR_S10;
 setit:
 			if ((ife->ifm_media & IFM_FDX) != 0) {
-				speed |= CIPHY_BMCR_FDX;
-				gig = CIPHY_1000CTL_AFD;
-			} else {
-				gig = CIPHY_1000CTL_AHD;
-			}
-
-			PHY_WRITE(sc, CIPHY_MII_1000CTL, 0);
-			PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
-			PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
+				speed |= BMCR_FDX;
+				gig = GTCR_ADV_1000TFDX;
+			} else
+				gig = GTCR_ADV_1000THDX;
+
+			PHY_WRITE(sc, MII_100T2CR, 0);
+			PHY_WRITE(sc, MII_BMCR, speed);
+			PHY_WRITE(sc, MII_ANAR, ANAR_CSMA);
 
 			if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
 				break;
 
-			PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
-			PHY_WRITE(sc, CIPHY_MII_BMCR,
-			    speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG);
+			PHY_WRITE(sc, MII_100T2CR, gig);
+			PHY_WRITE(sc, MII_BMCR,
+			    speed | BMCR_AUTOEN | BMCR_STARTNEG);
 
 			/*
 			 * When setting the link manually, one side must
@@ -224,38 +229,31 @@ setit:
 			 * be a master, otherwise it's a slave.
 			 */
 			if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
-				PHY_WRITE(sc, CIPHY_MII_1000CTL,
-				    gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC);
+				PHY_WRITE(sc, MII_100T2CR,
+				    gig | GTCR_MAN_MS | GTCR_ADV_MS);
 			} else {
-				PHY_WRITE(sc, CIPHY_MII_1000CTL,
-				    gig|CIPHY_1000CTL_MSE);
+				PHY_WRITE(sc, MII_100T2CR, gig | GTCR_MAN_MS);
 			}
 			break;
 		case IFM_NONE:
-			PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
+			PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
 			break;
 		case IFM_100_T4:
 		default:
-			return (EINVAL);
+			return EINVAL;
 		}
 		break;
 
 	case MII_TICK:
-		/*
-		 * If we're not currently selected, just return.
-		 */
+		/* If we're not currently selected, just return. */
 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
-			return (0);
+			return 0;
 
-		/*
-		 * Is the interface even up?
-		 */
+		/* Is the interface even up? */
 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
-			return (0);
+			return 0;
 
-		/*
-		 * Only used for autonegotiation.
-		 */
+		/* Only used for autonegotiation. */
 		if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) &&
 		    (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) {
 			/*
@@ -290,14 +288,12 @@ setit:
 		if (sc->mii_ticks++ == 0)
 			break;
 
-		/*
-		 * Only retry autonegotiation every N seconds.
-		 */
+		/* Only retry autonegotiation every N seconds. */
 		if (sc->mii_ticks <= MII_ANEGTICKS_GIGE)
 			break;
 
 		mii_phy_auto(sc, 0);
-		return (0);
+		return 0;
 	}
 
 	/* Update the media status. */
@@ -313,7 +309,7 @@ setit:
 		ciphy_fixup(sc);
 	}
 	mii_phy_update(sc, cmd);
-	return (0);
+	return 0;
 }
 
 static void
@@ -330,13 +326,13 @@ ciphy_status(struct mii_softc *sc)
 	if (bmsr & BMSR_LINK)
 		mii->mii_media_status |= IFM_ACTIVE;
 
-	bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
+	bmcr = PHY_READ(sc, MII_BMCR);
 
-	if (bmcr & CIPHY_BMCR_LOOP)
+	if (bmcr & BMCR_LOOP)
 		mii->mii_media_active |= IFM_LOOP;
 
-	if (bmcr & CIPHY_BMCR_AUTOEN) {
-		if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
+	if (bmcr & BMCR_AUTOEN) {
+		if ((bmsr & BMSR_ACOMP) == 0) {
 			/* Erg, still trying, I guess... */
 			mii->mii_media_active |= IFM_NONE;
 			return;
@@ -388,18 +384,19 @@ ciphy_fixup(struct mii_softc *sc)
 	uint16_t		model;
 	uint16_t		status, speed;
 
-	model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
+	model = MII_MODEL(PHY_READ(sc, MII_PHYIDR2));
 	status = PHY_READ(sc, CIPHY_MII_AUXCSR);
 	speed = status & CIPHY_AUXCSR_SPEED;
 
 	if (device_is_a(device_parent(sc->mii_dev), "nfe")) {
-		/* need to set for 2.5V RGMII for NVIDIA adapters */
+		/* Need to set for 2.5V RGMII for NVIDIA adapters */
 		PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_INTSEL_RGMII);
 		PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_IOVOL_2500MV);
 	}
 
 	switch (model) {
 	case MII_MODEL_CICADA_CS8201:
+	case MII_MODEL_CICADA_CS8204:
 
 		/* Turn off "aux mode" (whatever that means) */
 		PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
@@ -430,11 +427,14 @@ ciphy_fixup(struct mii_softc *sc)
 		if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
 		    (status & CIPHY_AUXCSR_FDX)) {
 			PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
-		} else {
+		} else
 			PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
-		}
 
 		break;
+	case MII_MODEL_CICADA_VSC8211:
+	case MII_MODEL_CICADA_CS8244:
+	case MII_MODEL_VITESSE_VSC8601:
+		break;
 	default:
 		aprint_error_dev(sc->mii_dev, "unknown CICADA PHY model %x\n",
 		    model);

Index: src/sys/dev/mii/ciphyreg.h
diff -u src/sys/dev/mii/ciphyreg.h:1.5 src/sys/dev/mii/ciphyreg.h:1.5.20.1
--- src/sys/dev/mii/ciphyreg.h:1.5	Mon Jun 16 14:43:22 2014
+++ src/sys/dev/mii/ciphyreg.h	Sun Sep  1 10:19:04 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: ciphyreg.h,v 1.5 2014/06/16 14:43:22 msaitoh Exp $ */
+/* $NetBSD: ciphyreg.h,v 1.5.20.1 2019/09/01 10:19:04 martin Exp $ */
 
 /*-
  * Copyright (c) 2004
@@ -42,134 +42,6 @@
  * PHY, embedded within the VIA Networks VT6122 controller.
  */
 
-/* Command register */
-#define CIPHY_MII_BMCR		0x00
-#define CIPHY_BMCR_RESET	0x8000
-#define CIPHY_BMCR_LOOP		0x4000
-#define CIPHY_BMCR_SPD0		0x2000	/* speed select, lower bit */
-#define CIPHY_BMCR_AUTOEN	0x1000	/* Autoneg enabled */
-#define CIPHY_BMCR_PDOWN	0x0800	/* Power down */
-#define CIPHY_BMCR_STARTNEG	0x0200	/* Restart autoneg */
-#define CIPHY_BMCR_FDX		0x0100	/* Duplex mode */
-#define CIPHY_BMCR_CTEST	0x0080	/* Collision test enable */
-#define CIPHY_BMCR_SPD1		0x0040	/* Speed select, upper bit */
-
-#define CIPHY_S1000		CIPHY_BMCR_SPD1	/* 1000mbps */
-#define CIPHY_S100		CIPHY_BMCR_SPD0	/* 100mpbs */
-#define CIPHY_S10		0		/* 10mbps */
-
-/* Status register */
-#define CIPHY_MII_BMSR		0x01
-#define CIPHY_BMSR_100T4	0x8000	/* 100 base T4 capable */
-#define CIPHY_BMSR_100TXFDX	0x4000	/* 100 base Tx full duplex capable */
-#define CIPHY_BMSR_100TXHDX	0x2000	/* 100 base Tx half duplex capable */
-#define CIPHY_BMSR_10TFDX	0x1000	/* 10 base T full duplex capable */
-#define CIPHY_BMSR_10THDX	0x0800	/* 10 base T half duplex capable */
-#define CIPHY_BMSR_100T2FDX	0x0400	/* 100 base T2 full duplex capable */
-#define CIPHY_BMSR_100T2HDX	0x0200	/* 100 base T2 half duplex capable */
-#define CIPHY_BMSR_EXTSTS	0x0100	/* Extended status present */
-#define CIPHY_BMSR_PRESUB	0x0040	/* Preamble surpression */
-#define CIPHY_BMSR_ACOMP	0x0020	/* Autoneg complete */
-#define CIPHY_BMSR_RFAULT	0x0010	/* Remote fault condition occured */
-#define CIPHY_BMSR_ANEG		0x0008	/* Autoneg capable */
-#define CIPHY_BMSR_LINK		0x0004	/* Link status */
-#define CIPHY_BMSR_JABBER	0x0002	/* Jabber detected */
-#define CIPHY_BMSR_EXT		0x0001	/* Extended capability */
-
-/* PHY ID registers */
-#define CIPHY_MII_PHYIDR1	0x02
-#define CIPHY_MII_PHYIDR2	0x03
-
-/* Autoneg advertisement */
-#define CIPHY_MII_ANAR		0x04
-#define CIPHY_ANAR_NP		0x8000	/* Next page */
-#define CIPHY_ANAR_RF		0x2000	/* Remote fault */
-#define CIPHY_ANAR_ASP		0x0800	/* Asymmetric Pause */
-#define CIPHY_ANAR_PC		0x0400	/* Pause capable */
-#define CIPHY_ANAR_T4		0x0200	/* local device supports 100bT4 */
-#define CIPHY_ANAR_TX_FD	0x0100	/* local device supports 100bTx FD */
-#define CIPHY_ANAR_TX		0x0080	/* local device supports 100bTx */
-#define CIPHY_ANAR_10_FD	0x0040	/* local device supports 10bT FD */
-#define CIPHY_ANAR_10		0x0020	/* local device supports 10bT */
-#define CIPHY_ANAR_SEL		0x001F	/* selector field, 00001=Ethernet */
-
-/* Autoneg link partner ability */
-#define CIPHY_MII_ANLPAR	0x05
-#define CIPHY_ANLPAR_NP		0x8000	/* Next page */
-#define CIPHY_ANLPAR_ACK	0x4000	/* link partner acknowledge */
-#define CIPHY_ANLPAR_RF		0x2000	/* Remote fault */
-#define CIPHY_ANLPAR_ASP	0x0800	/* Asymmetric Pause */
-#define CIPHY_ANLPAR_PC		0x0400	/* Pause capable */
-#define CIPHY_ANLPAR_T4		0x0200	/* link partner supports 100bT4 */
-#define CIPHY_ANLPAR_TX_FD	0x0100	/* link partner supports 100bTx FD */
-#define CIPHY_ANLPAR_TX		0x0080	/* link partner supports 100bTx */
-#define CIPHY_ANLPAR_10_FD	0x0040	/* link partner supports 10bT FD */
-#define CIPHY_ANLPAR_10		0x0020	/* link partner supports 10bT */
-#define CIPHY_ANLPAR_SEL	0x001F	/* selector field, 00001=Ethernet */
-
-#define CIPHY_SEL_TYPE		0x0001	/* ethernet */
-
-/* Antoneg expansion register */
-#define CIPHY_MII_ANER		0x06
-#define CIPHY_ANER_PDF		0x0010	/* Parallel detection fault */
-#define CIPHY_ANER_LPNP		0x0008	/* Link partner can next page */
-#define CIPHY_ANER_NP		0x0004	/* Local PHY can next page */
-#define CIPHY_ANER_RX		0x0002	/* Next page received */
-#define CIPHY_ANER_LPAN		0x0001 	/* Link partner autoneg capable */
-
-/* Autoneg next page transmit regisyer */
-#define CIPHY_MII_NEXTP		0x07
-#define CIPHY_NEXTP_MOREP	0x8000	/* More pages to follow */
-#define CIPHY_NEXTP_MESS	0x2000	/* 1 = message page, 0 = unformatted */
-#define CIPHY_NEXTP_ACK2	0x1000	/* MAC acknowledge */
-#define CIPHY_NEXTP_TOGGLE	0x0800	/* Toggle */
-#define CIPHY_NEXTP_CODE	0x07FF	/* Code bits */
-
-/* Autoneg link partner next page receive register */
-#define CIPHY_MII_NEXTP_LP	0x08
-#define CIPHY_NEXTPLP_MOREP	0x8000	/* More pages to follow */
-#define CIPHY_NEXTPLP_MESS	0x2000	/* 1 = message page, 0 = unformatted */
-#define CIPHY_NEXTPLP_ACK2	0x1000	/* MAC acknowledge */
-#define CIPHY_NEXTPLP_TOGGLE	0x0800	/* Toggle */
-#define CIPHY_NEXTPLP_CODE	0x07FF	/* Code bits */
-
-/* 1000BT control register */
-#define CIPHY_MII_1000CTL	0x09
-#define CIPHY_1000CTL_TST	0xE000	/* test modes */
-#define CIPHY_1000CTL_MSE	0x1000	/* Master/Slave manual enable */
-#define CIPHY_1000CTL_MSC	0x0800	/* Master/Slave select */
-#define CIPHY_1000CTL_RD	0x0400	/* Repeater/DTE */
-#define CIPHY_1000CTL_AFD	0x0200	/* Advertise full duplex */
-#define CIPHY_1000CTL_AHD	0x0100	/* Advertise half duplex */
-
-#define CIPHY_TEST_TX_JITTER			0x2000
-#define CIPHY_TEST_TX_JITTER_MASTER_MODE	0x4000
-#define CIPHY_TEST_TX_JITTER_SLAVE_MODE		0x6000
-#define CIPHY_TEST_TX_DISTORTION		0x8000
-
-/* 1000BT status register */
-#define CIPHY_MII_1000STS	0x0A
-#define CIPHY_1000STS_MSF	0x8000	/* Master/slave fault */
-#define CIPHY_1000STS_MSR	0x4000	/* Master/slave result */
-#define CIPHY_1000STS_LRS	0x2000	/* Local receiver status */
-#define CIPHY_1000STS_RRS	0x1000	/* Remote receiver status */
-#define CIPHY_1000STS_LPFD	0x0800	/* Link partner can FD */
-#define CIPHY_1000STS_LPHD	0x0400	/* Link partner can HD */
-#define CIPHY_1000STS_IEC	0x00FF	/* Idle error count */
-
-#define CIPHY_MII_EXTSTS	0x0F	/* Extended status */
-#define CIPHY_EXTSTS_X_FD_CAP	0x8000	/* 1000base-X FD capable */
-#define CIPHY_EXTSTS_X_HD_CAP	0x4000	/* 1000base-X HD capable */
-#define CIPHY_EXTSTS_T_FD_CAP	0x2000	/* 1000base-T FD capable */
-#define CIPHY_EXTSTS_T_HD_CAP	0x1000	/* 1000base-T HD capable */
-
-/* 1000BT status extension register #1 */
-#define CIPHY_MII_1000STS1	0x0F
-#define CIPHY_1000STS1_1000XFDX	0x8000	/* 1000baseX FDX capable */
-#define CIPHY_1000STS1_1000XHDX	0x4000	/* 1000baseX HDX capable */
-#define CIPHY_1000STS1_1000TFDX	0x2000	/* 1000baseT FDX capable */
-#define CIPHY_1000STS1_1000THDX	0x1000	/* 1000baseT HDX capable */
-
 /* Vendor-specific PHY registers */
 
 /* 100baseTX status extension register */

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