Module Name: src Committed By: jmcneill Date: Sat Oct 19 18:04:26 UTC 2019
Modified Files: src/sys/arch/aarch64/aarch64: cpu.c locore.S src/sys/arch/aarch64/include: cpu.h param.h src/sys/arch/arm/acpi: cpu_acpi.c src/sys/arch/arm/arm32: cpu.c src/sys/arch/arm/fdt: cpu_fdt.c src/sys/arch/arm/include: cpu.h Log Message: Increase aarch64 MAXCPUS to 256. To generate a diff of this commit: cvs rdiff -u -r1.22 -r1.23 src/sys/arch/aarch64/aarch64/cpu.c cvs rdiff -u -r1.41 -r1.42 src/sys/arch/aarch64/aarch64/locore.S cvs rdiff -u -r1.13 -r1.14 src/sys/arch/aarch64/include/cpu.h cvs rdiff -u -r1.11 -r1.12 src/sys/arch/aarch64/include/param.h cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/acpi/cpu_acpi.c cvs rdiff -u -r1.132 -r1.133 src/sys/arch/arm/arm32/cpu.c cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/fdt/cpu_fdt.c cvs rdiff -u -r1.100 -r1.101 src/sys/arch/arm/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/aarch64/aarch64/cpu.c diff -u src/sys/arch/aarch64/aarch64/cpu.c:1.22 src/sys/arch/aarch64/aarch64/cpu.c:1.23 --- src/sys/arch/aarch64/aarch64/cpu.c:1.22 Mon Oct 14 22:53:05 2019 +++ src/sys/arch/aarch64/aarch64/cpu.c Sat Oct 19 18:04:26 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.c,v 1.22 2019/10/14 22:53:05 jmcneill Exp $ */ +/* $NetBSD: cpu.c,v 1.23 2019/10/19 18:04:26 jmcneill Exp $ */ /* * Copyright (c) 2017 Ryo Shimizu <r...@nerv.org> @@ -27,7 +27,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.22 2019/10/14 22:53:05 jmcneill Exp $"); +__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.23 2019/10/19 18:04:26 jmcneill Exp $"); #include "locators.h" #include "opt_arm_debug.h" @@ -69,8 +69,9 @@ static void cpu_setup_sysctl(device_t, s #ifdef MULTIPROCESSOR uint64_t cpu_mpidr[MAXCPUS]; -volatile u_int arm_cpu_hatched __cacheline_aligned = 0; -volatile uint32_t arm_cpu_mbox __cacheline_aligned = 0; +volatile u_int aarch64_cpu_mbox[MAXCPUS] __cacheline_aligned = { 0 }; +#define CPU_MBOX_HATCHED __BIT(0) +#define CPU_MBOX_START __BIT(1) u_int arm_cpu_max = 1; static kmutex_t cpu_hatch_lock; @@ -126,7 +127,7 @@ cpu_attach(device_t dv, cpuid_t id) /* ci_id is stored by own cpus when hatching */ cpu_info[ncpu] = ci; - if ((arm_cpu_hatched & __BIT(unit)) == 0) { + if (cpu_hatched_p(unit) == 0) { ci->ci_dev = dv; dv->dv_private = ci; ci->ci_index = -1; @@ -499,27 +500,35 @@ cpu_setup_sysctl(device_t dv, struct cpu void cpu_boot_secondary_processors(void) { + u_int cpuno; + if ((boothowto & RB_MD1) != 0) return; mutex_init(&cpu_hatch_lock, MUTEX_DEFAULT, IPL_NONE); - VPRINTF("%s: writing mbox with %#x\n", __func__, arm_cpu_hatched); + VPRINTF("%s: starting secondary processors\n", __func__); /* send mbox to have secondary processors do cpu_hatch() */ - atomic_or_32(&arm_cpu_mbox, arm_cpu_hatched); + for (cpuno = 1; cpuno < ncpu; cpuno++) { + if (cpu_hatched_p(cpuno) == false) + continue; + atomic_or_uint(&aarch64_cpu_mbox[cpuno], CPU_MBOX_START); + } __asm __volatile ("sev; sev; sev"); /* wait all cpus have done cpu_hatch() */ - while (membar_consumer(), arm_cpu_mbox & arm_cpu_hatched) { - __asm __volatile ("wfe"); + for (cpuno = 1; cpuno < ncpu; cpuno++) { + if (cpu_hatched_p(cpuno) == 0) + continue; + while (membar_consumer(), aarch64_cpu_mbox[cpuno] & CPU_MBOX_START) { + __asm __volatile ("wfe"); + } + /* Add processor to kcpuset */ + kcpuset_set(kcpuset_attached, cpuno); } VPRINTF("%s: secondary processors hatched\n", __func__); - - /* add available processors to kcpuset */ - uint32_t mbox = arm_cpu_hatched; - kcpuset_export_u32(kcpuset_attached, &mbox, sizeof(mbox)); } void @@ -549,12 +558,20 @@ cpu_hatch(struct cpu_info *ci) #endif /* - * clear my bit of arm_cpu_mbox to tell cpu_boot_secondary_processors(). + * clear my bit of aarch64_cpu_mbox to tell cpu_boot_secondary_processors(). * there are cpu0,1,2,3, and if cpu2 is unresponsive, * ci_index are each cpu0=0, cpu1=1, cpu2=undef, cpu3=2. * therefore we have to use device_unit instead of ci_index for mbox. */ - atomic_and_32(&arm_cpu_mbox, ~__BIT(device_unit(ci->ci_dev))); + const u_int cpuno = device_unit(ci->ci_dev); + atomic_and_uint(&aarch64_cpu_mbox[cpuno], ~(u_int)CPU_MBOX_START); __asm __volatile ("sev; sev; sev"); } + +bool +cpu_hatched_p(u_int cpuindex) +{ + membar_consumer(); + return (aarch64_cpu_mbox[cpuindex] & CPU_MBOX_HATCHED) != 0; +} #endif /* MULTIPROCESSOR */ Index: src/sys/arch/aarch64/aarch64/locore.S diff -u src/sys/arch/aarch64/aarch64/locore.S:1.41 src/sys/arch/aarch64/aarch64/locore.S:1.42 --- src/sys/arch/aarch64/aarch64/locore.S:1.41 Sun Sep 29 08:33:20 2019 +++ src/sys/arch/aarch64/aarch64/locore.S Sat Oct 19 18:04:26 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.41 2019/09/29 08:33:20 skrll Exp $ */ +/* $NetBSD: locore.S,v 1.42 2019/10/19 18:04:26 jmcneill Exp $ */ /* * Copyright (c) 2017 Ryo Shimizu <r...@nerv.org> @@ -38,7 +38,7 @@ #include <aarch64/hypervisor.h> #include "assym.h" -RCSID("$NetBSD: locore.S,v 1.41 2019/09/29 08:33:20 skrll Exp $") +RCSID("$NetBSD: locore.S,v 1.42 2019/10/19 18:04:26 jmcneill Exp $") /*#define DEBUG_LOCORE /* debug print */ @@ -368,13 +368,12 @@ ENTRY_NP(cpu_mpstart) bne 1b mov x27, x1 /* x27 = cpuindex */ - mov x0, #1 - lsl x28, x0, x27 /* x28 = 1 << cpuindex */ - + ADDR x0, _C_LABEL(aarch64_cpu_mbox) + add x28, x0, x27, lsl #2 /* x28 = &aarch64_cpu_mbox[cpuindex] */ /* * x27 = cpuindex - * x28 = (1 << cpuindex) + * x28 = &aarch64_cpu_mbox[cpuindex] */ /* set stack pointer for boot */ @@ -447,28 +446,25 @@ mp_vstart: mrs x1, mpidr_el1 str x1, [x0, #CI_MPIDR] /* curcpu()->ci_mpidr = mpidr_el1 */ - CPU_DPRINTREG("arm_cpu_hatched |= ", x28) - /* - * atomic_or_32(&arm_cpu_hatched, (1 << cpuindex)) + * atomic_or_uint(&aarch64_cpu_mbox[cpuindex], 1) * to tell my activity to primary processor. */ - ADDR x0, _C_LABEL(arm_cpu_hatched) - mov x1, x28 - bl _C_LABEL(atomic_or_32) /* hatched! */ + mov x0, x28 + mov x1, #1 + bl _C_LABEL(atomic_or_uint) /* hatched! */ + dsb sy sev - /* wait for my bit of arm_cpu_mbox become true */ - ADDR x0, _C_LABEL(arm_cpu_mbox) + /* wait for the mailbox start bit to become true */ 1: dmb sy - ldr x20, [x0] - tst x20, x28 + ldr x20, [x28] + tst x20, #2 bne 9f wfe b 1b 9: -// CPU_DPRINTREG("got arm_cpu_mbox = ", x20) /* fill my cpu_info */ mrs x0, tpidr_el1 /* curcpu() */ Index: src/sys/arch/aarch64/include/cpu.h diff -u src/sys/arch/aarch64/include/cpu.h:1.13 src/sys/arch/aarch64/include/cpu.h:1.14 --- src/sys/arch/aarch64/include/cpu.h:1.13 Fri Dec 21 08:01:01 2018 +++ src/sys/arch/aarch64/include/cpu.h Sat Oct 19 18:04:26 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.h,v 1.13 2018/12/21 08:01:01 ryo Exp $ */ +/* $NetBSD: cpu.h,v 1.14 2019/10/19 18:04:26 jmcneill Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -126,8 +126,8 @@ void cpu_mpstart(void); void cpu_hatch(struct cpu_info *); extern struct cpu_info *cpu_info[]; -extern volatile u_int arm_cpu_hatched; /* MULTIPROCESSOR */ extern uint64_t cpu_mpidr[]; /* MULTIPROCESSOR */ +bool cpu_hatched_p(u_int); /* MULTIPROCESSOR */ #define CPU_INFO_ITERATOR cpuid_t #ifdef MULTIPROCESSOR Index: src/sys/arch/aarch64/include/param.h diff -u src/sys/arch/aarch64/include/param.h:1.11 src/sys/arch/aarch64/include/param.h:1.12 --- src/sys/arch/aarch64/include/param.h:1.11 Sat Jan 19 09:11:55 2019 +++ src/sys/arch/aarch64/include/param.h Sat Oct 19 18:04:26 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: param.h,v 1.11 2019/01/19 09:11:55 skrll Exp $ */ +/* $NetBSD: param.h,v 1.12 2019/10/19 18:04:26 jmcneill Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -129,6 +129,8 @@ #define COHERENCY_UNIT 128 #define CACHE_LINE_SIZE 128 +#define MAXCPUS 256 + #ifdef _KERNEL #ifndef __HIDE_DELAY Index: src/sys/arch/arm/acpi/cpu_acpi.c diff -u src/sys/arch/arm/acpi/cpu_acpi.c:1.6 src/sys/arch/arm/acpi/cpu_acpi.c:1.7 --- src/sys/arch/arm/acpi/cpu_acpi.c:1.6 Thu May 23 15:54:28 2019 +++ src/sys/arch/arm/acpi/cpu_acpi.c Sat Oct 19 18:04:26 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu_acpi.c,v 1.6 2019/05/23 15:54:28 ryo Exp $ */ +/* $NetBSD: cpu_acpi.c,v 1.7 2019/10/19 18:04:26 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -33,7 +33,7 @@ #include "opt_multiprocessor.h" #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: cpu_acpi.c,v 1.6 2019/05/23 15:54:28 ryo Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cpu_acpi.c,v 1.7 2019/10/19 18:04:26 jmcneill Exp $"); #include <sys/param.h> #include <sys/bus.h> @@ -41,6 +41,7 @@ __KERNEL_RCSID(0, "$NetBSD: cpu_acpi.c,v #include <sys/device.h> #include <sys/interrupt.h> #include <sys/kcpuset.h> +#include <sys/reboot.h> #include <dev/acpi/acpireg.h> #include <dev/acpi/acpivar.h> @@ -99,7 +100,7 @@ cpu_acpi_attach(device_t parent, device_ struct cpu_info *ci = &cpu_info_store[unit]; #ifdef MULTIPROCESSOR - if (cpu_mpidr_aff_read() != mpidr) { + if (cpu_mpidr_aff_read() != mpidr && (boothowto & RB_MD1) == 0) { const u_int cpuindex = device_unit(self); int error; @@ -116,9 +117,8 @@ cpu_acpi_attach(device_t parent, device_ __asm __volatile("sev" ::: "memory"); for (u_int i = 0x10000000; i > 0; i--) { - membar_consumer(); - if (arm_cpu_hatched & __BIT(cpuindex)) - break; + if (cpu_hatched_p(cpuindex)) + break; } } #endif /* MULTIPROCESSOR */ Index: src/sys/arch/arm/arm32/cpu.c diff -u src/sys/arch/arm/arm32/cpu.c:1.132 src/sys/arch/arm/arm32/cpu.c:1.133 --- src/sys/arch/arm/arm32/cpu.c:1.132 Sun Sep 29 06:51:45 2019 +++ src/sys/arch/arm/arm32/cpu.c Sat Oct 19 18:04:26 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.c,v 1.132 2019/09/29 06:51:45 skrll Exp $ */ +/* $NetBSD: cpu.c,v 1.133 2019/10/19 18:04:26 jmcneill Exp $ */ /* * Copyright (c) 1995 Mark Brinicombe. @@ -46,7 +46,7 @@ #include "opt_multiprocessor.h" #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.132 2019/09/29 06:51:45 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.133 2019/10/19 18:04:26 jmcneill Exp $"); #include <sys/param.h> #include <sys/conf.h> @@ -130,7 +130,7 @@ cpu_attach(device_t dv, cpuid_t id) ci->ci_undefsave[2] = cpu_info_store.ci_undefsave[2]; cpu_info[unit] = ci; - if ((arm_cpu_hatched & __BIT(unit)) == 0) { + if (cpu_hatched_p(unit) == false) { ci->ci_dev = dv; dv->dv_private = ci; aprint_naive(": disabled\n"); @@ -239,6 +239,13 @@ cpu_attach(device_t dv, cpuid_t id) vfp_attach(ci); /* XXX SMP */ } +bool +cpu_hatched_p(u_int cpuindex) +{ + membar_consumer(); + return (arm_cpu_hatched & __BIT(cpuindex)) != 0; +} + enum cpu_class { CPU_CLASS_NONE, CPU_CLASS_ARM2, Index: src/sys/arch/arm/fdt/cpu_fdt.c diff -u src/sys/arch/arm/fdt/cpu_fdt.c:1.27 src/sys/arch/arm/fdt/cpu_fdt.c:1.28 --- src/sys/arch/arm/fdt/cpu_fdt.c:1.27 Thu Oct 17 21:52:26 2019 +++ src/sys/arch/arm/fdt/cpu_fdt.c Sat Oct 19 18:04:26 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu_fdt.c,v 1.27 2019/10/17 21:52:26 bad Exp $ */ +/* $NetBSD: cpu_fdt.c,v 1.28 2019/10/19 18:04:26 jmcneill Exp $ */ /*- * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca> @@ -30,7 +30,7 @@ #include "psci_fdt.h" #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: cpu_fdt.c,v 1.27 2019/10/17 21:52:26 bad Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cpu_fdt.c,v 1.28 2019/10/19 18:04:26 jmcneill Exp $"); #include <sys/param.h> #include <sys/atomic.h> @@ -308,8 +308,7 @@ arm_fdt_cpu_mpstart(void) /* Wait for AP to start */ for (i = 0x10000000; i > 0; i--) { - membar_consumer(); - if (arm_cpu_hatched & __BIT(cpuindex)) + if (cpu_hatched_p(cpuindex)) break; } Index: src/sys/arch/arm/include/cpu.h diff -u src/sys/arch/arm/include/cpu.h:1.100 src/sys/arch/arm/include/cpu.h:1.101 --- src/sys/arch/arm/include/cpu.h:1.100 Thu Jan 3 10:26:41 2019 +++ src/sys/arch/arm/include/cpu.h Sat Oct 19 18:04:26 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.h,v 1.100 2019/01/03 10:26:41 skrll Exp $ */ +/* $NetBSD: cpu.h,v 1.101 2019/10/19 18:04:26 jmcneill Exp $ */ /* * Copyright (c) 1994-1996 Mark Brinicombe. @@ -253,8 +253,8 @@ extern struct cpu_info *cpu_info[]; #if defined(MULTIPROCESSOR) -extern volatile u_int arm_cpu_hatched; extern uint32_t cpu_mpidr[]; +bool cpu_hatched_p(u_int); void cpu_mpstart(void); void cpu_init_secondary_processor(int);