Module Name: src
Committed By: matt
Date: Thu Aug 6 01:27:48 UTC 2009
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
Add Loongson2 support.
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/mips/mips/cache.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/cache.c
diff -u src/sys/arch/mips/mips/cache.c:1.33 src/sys/arch/mips/mips/cache.c:1.34
--- src/sys/arch/mips/mips/cache.c:1.33 Sat Dec 24 23:24:01 2005
+++ src/sys/arch/mips/mips/cache.c Thu Aug 6 01:27:47 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.c,v 1.33 2005/12/24 23:24:01 perry Exp $ */
+/* $NetBSD: cache.c,v 1.34 2009/08/06 01:27:47 matt Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.33 2005/12/24 23:24:01 perry Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.34 2009/08/06 01:27:47 matt Exp $");
#include "opt_cputype.h"
#include "opt_mips_cache.h"
@@ -652,7 +652,38 @@
break;
#endif /* ENABLE_MIPS4_CACHE_R10K */
#endif /* MIPS3 || MIPS4 */
+#ifdef MIPS64_LOONGSON2
+ case MIPS_LOONGSON2:
+ mips_picache_ways = 4;
+ mips_pdcache_ways = 4;
+ mips_picache_size = 64*1024;
+ mips_pdcache_size = 64*1024;
+
+ mips_picache_line_size = 32;
+ mips_pdcache_line_size = 32;
+
+ mips_cache_ops.mco_icache_sync_all =
+ r4k_icache_sync_all_32;
+ mips_cache_ops.mco_icache_sync_range =
+ r4k_icache_sync_range_32;
+ mips_cache_ops.mco_icache_sync_range_index =
+ r4k_icache_sync_range_index_32;
+
+ mips_cache_ops.mco_pdcache_wbinv_all =
+ r4k_pdcache_wbinv_all_32;
+ mips_cache_ops.mco_pdcache_wbinv_range =
+ r4k_pdcache_wbinv_range_32;
+ mips_cache_ops.mco_pdcache_wbinv_range_index =
+ r4k_pdcache_wbinv_range_index_32;
+ mips_cache_ops.mco_pdcache_inv_range =
+ r4k_pdcache_inv_range_32;
+ mips_cache_ops.mco_pdcache_wb_range =
+ r4k_pdcache_wb_range_32;
+
+ /* Virtually-indexed cache; no use for colors. */
+ break;
+#endif
default:
panic("can't handle primary cache on impl 0x%x",
MIPS_PRID_IMPL(cpu_id));
@@ -797,6 +828,24 @@
break;
#endif /* ENABLE_MIPS4_CACHE_R10K */
#endif /* MIPS3 || MIPS4 */
+#ifdef MIPS64_LOONGSON2
+ case MIPS_LOONGSON2:
+ mips_sdcache_ways = 4;
+ mips_sdcache_size = 512*1024;
+ mips_sdcache_line_size = 32;
+
+ mips_cache_ops.mco_sdcache_wbinv_all =
+ r4k_sdcache_wbinv_all_32;
+ mips_cache_ops.mco_sdcache_wbinv_range =
+ r4k_sdcache_wbinv_range_32;
+ mips_cache_ops.mco_sdcache_wbinv_range_index =
+ r4k_sdcache_wbinv_range_index_32;
+ mips_cache_ops.mco_sdcache_inv_range =
+ r4k_sdcache_inv_range_32;
+ mips_cache_ops.mco_sdcache_wb_range =
+ r4k_sdcache_wb_range_32;
+ break;
+#endif
default:
panic("can't handle secondary cache on impl 0x%x",
