Module Name: src Committed By: matt Date: Fri Aug 7 23:23:58 UTC 2009
Modified Files: src/sys/arch/mips/mips: cache_ls2.c Log Message: Clean up a bit. No reason to use 4way on icache ops (it clears all ways). To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/mips/cache_ls2.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/mips/mips/cache_ls2.c diff -u src/sys/arch/mips/mips/cache_ls2.c:1.1 src/sys/arch/mips/mips/cache_ls2.c:1.2 --- src/sys/arch/mips/mips/cache_ls2.c:1.1 Fri Aug 7 18:39:10 2009 +++ src/sys/arch/mips/mips/cache_ls2.c Fri Aug 7 23:23:58 2009 @@ -1,4 +1,4 @@ -/* $NetBSD: cache_ls2.c,v 1.1 2009/08/07 18:39:10 matt Exp $ */ +/* $NetBSD: cache_ls2.c,v 1.2 2009/08/07 23:23:58 matt Exp $ */ /*- * Copyright (c) 2009 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: cache_ls2.c,v 1.1 2009/08/07 18:39:10 matt Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cache_ls2.c,v 1.2 2009/08/07 23:23:58 matt Exp $"); #include <sys/param.h> @@ -59,24 +59,19 @@ va = trunc_line(va); - if (va + mips_picache_way_size <= eva) { + if (va + mips_picache_size <= eva) { ls2_icache_sync_all(); return; } -#if 0 - mips_dcache_wb_range(va, (eva - va)); -#endif - - while (va + 8 * 32 <= eva) { - cache_op_ls2_8line_4way(va, CACHEOP_LS2_D_HIT_WB_INV); - cache_op_ls2_8line_4way(va, CACHEOP_LS2_I_INDEX_INV); - va += 8 * 32; + + for (; va + 8 * 32 <= eva; va += 8 * 32) { + cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_WB_INV); + cache_op_ls2_8line(va, CACHEOP_LS2_I_INDEX_INV); } - while (va < eva) { - cache_op_ls2_line_4way(va, CACHEOP_LS2_D_HIT_WB_INV); - cache_op_ls2_line_4way(va, CACHEOP_LS2_I_INDEX_INV); - va += 32; + for (; va < eva; va += 32) { + cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_WB_INV); + cache_op_ls2_line(va, CACHEOP_LS2_I_INDEX_INV); } __asm volatile("sync"); @@ -103,22 +98,17 @@ eva = mips_picache_way_size; } -#if 0 - mips_dcache_wbinv_range_index(va, (eva - va)); - __asm volatile("sync"); -#endif - - while (va + 8 * 32 <= eva) { + for (; va + 8 * 32 <= eva; va += 8 * 32) { cache_op_ls2_8line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV); - cache_op_ls2_8line_4way(va, CACHEOP_LS2_I_INDEX_INV); - va += 8 * 32; + cache_op_ls2_8line(va, CACHEOP_LS2_I_INDEX_INV); } - while (va < eva) { + for (; va < eva; va += 32) { cache_op_ls2_line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV); - cache_op_ls2_line_4way(va, CACHEOP_LS2_I_INDEX_INV); - va += 32; + cache_op_ls2_line(va, CACHEOP_LS2_I_INDEX_INV); } + + __asm volatile("sync"); } void @@ -134,15 +124,15 @@ va = trunc_line(va); - while (va + 8 * 32 <= eva) { + for (; va + 8 * 32 <= eva; va += 8 * 32) { cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_INV); - va += 8 * 32; } - while (va < eva) { + for (; va < eva; va += 32) { cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_INV); - va += 32; } + + __asm volatile("sync"); } void @@ -152,15 +142,15 @@ va = trunc_line(va); - while (va + 8 * 32 <= eva) { + for (; va + 8 * 32 <= eva; va += 8 * 32) { cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_WB_INV); - va += 8 * 32; } - while (va < eva) { + for (; va < eva; va += 32) { cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_WB_INV); - va += 32; } + + __asm volatile("sync"); } void @@ -193,15 +183,15 @@ eva = mips_pdcache_way_size; } - while (va + 8 * 32 <= eva) { + for (; va + 8 * 32 <= eva; va += 8 * 32) { cache_op_ls2_8line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV); - va += 8 * 32; } - while (va < eva) { + for (; va < eva; va += 32) { cache_op_ls2_line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV); - va += 32; } + + __asm volatile("sync"); } void @@ -226,15 +216,15 @@ va = trunc_line(va); - while (va + 8 * 32 <= eva) { + for (; va + 8 * 32 <= eva; va += 8 * 32) { cache_op_ls2_8line(va, CACHEOP_LS2_S_HIT_INV); - va += 8 * 32; } - while (va < eva) { + for (; va < eva; va += 32) { cache_op_ls2_line(va, CACHEOP_LS2_S_HIT_INV); - va += 32; } + + __asm volatile("sync"); } void @@ -244,15 +234,15 @@ va = trunc_line(va); - while (va + 8 * 32 <= eva) { + for (; va + 8 * 32 <= eva; va += 8 * 32) { cache_op_ls2_8line(va, CACHEOP_LS2_S_HIT_WB_INV); - va += 8 * 32; } - while (va < eva) { + for (; va < eva; va += 32) { cache_op_ls2_line(va, CACHEOP_LS2_S_HIT_WB_INV); - va += 32; } + + __asm volatile("sync"); } void @@ -285,15 +275,15 @@ eva = va + mips_sdcache_way_size; } - while (va + 8 * 32 <= eva) { + for (; va + 8 * 32 <= eva; va += 8 * 32) { cache_op_ls2_8line_4way(va, CACHEOP_LS2_S_INDEX_WB_INV); - va += 8 * 32; } - while (va < eva) { + for (; va < eva; va += 32) { cache_op_ls2_line_4way(va, CACHEOP_LS2_S_INDEX_WB_INV); - va += 32; } + + __asm volatile("sync"); } void