Module Name: src
Committed By: mrg
Date: Sat Nov 28 21:07:02 UTC 2009
Modified Files:
src/sys/arch/sparc64/include: ctlreg.h
Log Message:
add some ultrasparcIII defines, from openbsd.
To generate a diff of this commit:
cvs rdiff -u -r1.45 -r1.46 src/sys/arch/sparc64/include/ctlreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/include/ctlreg.h
diff -u src/sys/arch/sparc64/include/ctlreg.h:1.45 src/sys/arch/sparc64/include/ctlreg.h:1.46
--- src/sys/arch/sparc64/include/ctlreg.h:1.45 Sat May 16 19:15:34 2009
+++ src/sys/arch/sparc64/include/ctlreg.h Sat Nov 28 21:07:02 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: ctlreg.h,v 1.45 2009/05/16 19:15:34 nakayama Exp $ */
+/* $NetBSD: ctlreg.h,v 1.46 2009/11/28 21:07:02 mrg Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath
@@ -63,6 +63,10 @@
#define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */
#define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */
+#define ASI_DCACHE_INVALIDATE 0x42 /* [III] invalidate D-cache */
+#define ASI_DCACHE_UTAG 0x43 /* [III] diagnostic access to D-cache micro tag */
+#define ASI_DCACHE_SNOOP_TAG 0x44 /* [III] diagnostic access to D-cache snoop tag RAM */
+
#define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */
#define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */
@@ -244,6 +248,7 @@
/*
* The following are the control registers
* They work on both MMUs unless noted.
+ * III = cheetah only
*
* Register contents are defined later on individual registers.
*/
@@ -257,6 +262,9 @@
#define TLB_TAG_ACCESS 0x30
#define VIRTUAL_WATCHPOINT 0x38
#define PHYSICAL_WATCHPOINT 0x40
+#define TSB_PEXT 0x48 /* III primary ext */
+#define TSB_SEXT 0x50 /* III 2ndary ext -- DMMU only */
+#define TSB_NEXT 0x58 /* III nucleus ext */
/* Tag Target bits */
#define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL
