Module Name: src
Committed By: skrll
Date: Wed Jan 2 16:17:15 UTC 2019
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
Log Message:
Misc. tidyup
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/arm/armv6_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.2 src/sys/arch/arm/arm/armv6_start.S:1.3
--- src/sys/arch/arm/arm/armv6_start.S:1.2 Wed Jan 2 14:31:33 2019
+++ src/sys/arch/arm/arm/armv6_start.S Wed Jan 2 16:17:15 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.2 2019/01/02 14:31:33 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.3 2019/01/02 16:17:15 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -667,16 +667,15 @@ armv7_mmuinit:
#if 0
-//XXXNH FreeBSD
-288 /*
-289 * Set TEX remap registers
-290 * - All is set to uncacheable memory
-291 */
-292 ldr r0, =0xAAAAA
-293 mcr CP15_PRRR(r0)
-294 mov r0, #0
-295 mcr CP15_NMRR(r0)
+/*
+ * Set TEX remap registers
+ * - All is set to uncacheable memory
+ */
+ ldr r0, =0xAAAAA
+ mcr CP15_PRRR(r0)
+ mov r0, #0
+ mcr CP15_NMRR(r0)
#endif
XPUTC(#'I')
@@ -758,16 +757,6 @@ ENTRY_NP(cpu_mpstart)
XPUTC('\n')
XPUTC('\r')
-#if 0
- // We haven't used anything from memory yet so we can invalidate the
- // L1 cache without fear of losing valuable data. Afterwards, we can
- // flush icache without worrying about anything getting written back
- // to memory.
- bl armv7_dcache_l1inv_all // toss-dcache
- bl armv7_icache_inv_all // toss i-cache after d-cache
-
-#endif
-
// disables and clears caches
bl armv7_init
@@ -970,13 +959,6 @@ armv6_mmuinit:
nop
nop
-#if 0
- VPRINTF("MMU\n\r")
-
- VPRINTX(r4)
- VPRINTF("\n\r")
-#endif
-
mov pc, r4
.ltorg
