Module Name: src
Committed By: skrll
Date: Wed Jan 2 16:27:04 UTC 2019
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
Log Message:
Whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/arm/armv6_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.3 src/sys/arch/arm/arm/armv6_start.S:1.4
--- src/sys/arch/arm/arm/armv6_start.S:1.3 Wed Jan 2 16:17:15 2019
+++ src/sys/arch/arm/arm/armv6_start.S Wed Jan 2 16:27:04 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.3 2019/01/02 16:17:15 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.4 2019/01/02 16:27:04 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -480,6 +480,7 @@ generic_startv6:
#else
#define CPU_CONTROL_EX_BEND_SET CPU_CONTROL_EX_BEND
#endif
+
#ifdef ARM32_DISABLE_ALIGNMENT_FAULTS
#define CPU_CONTROL_AFLT_ENABLE_CLR CPU_CONTROL_AFLT_ENABLE
#define CPU_CONTROL_AFLT_ENABLE_SET 0
@@ -487,6 +488,7 @@ generic_startv6:
#define CPU_CONTROL_AFLT_ENABLE_CLR 0
#define CPU_CONTROL_AFLT_ENABLE_SET CPU_CONTROL_AFLT_ENABLE
#endif
+
#ifdef ARM_MMU_EXTENDED
#define CPU_CONTROL_XP_ENABLE_CLR 0
#define CPU_CONTROL_XP_ENABLE_SET CPU_CONTROL_XP_ENABLE
@@ -760,7 +762,6 @@ ENTRY_NP(cpu_mpstart)
// disables and clears caches
bl armv7_init
-
movw r0, #:lower16:TEMP_L1_TABLE
movt r0, #:upper16:TEMP_L1_TABLE
sub r0, R_VTOPDIFF
