Module Name: src
Committed By: martin
Date: Thu Jan 17 17:23:03 UTC 2019
Modified Files:
src/sys/dev/mii [netbsd-8]: makphy.c makphyreg.h miidevs
Log Message:
Pull up the following (requested by msaitoh in ticket #1164):
sys/dev/mii/miidevs 1.128, 1.132 (patch)
sys/dev/mii/makphy.c 1.43-1.51
sys/dev/mii/makphyreg.h 1.7-1.9
- miidevs: Add E1000 with model id 0x0006, it exists according to
OpenBSD rename E1000 model 0x0000 to E1000_0 for consistency.
- Match 88E1112, 88E1118, 88E1512, 88E3082 and G65G.
- Match 88E3016 and add some 88E3016 specific code. Fixes part of
PR kern/49270 and PR kern/53301.
- Make sure page 0 is selected when we initialize the PHY. Fixes
problems with the eephy(4) that attaches to nfe(4) on machines like
the Sun Ultra 40. (we had condition for this, now the page 0 is
selected for any PHY type)
- If autonegotiation is not enabled, we need a software reset for the
settings to take effect in makphy_service().
- Don't set PSCR_CRS_ON_TX on newer. Those chips have no this bit.
- Control BMCR_PDOWN for IFM_NONE. Some chips still don't work as
expected. It would be required to modify PSCR and/or other register.
- Set mii_media_active correctly on non-autonego mode.
- Remove obsolete comment.
- Whitespace fix.
To generate a diff of this commit:
cvs rdiff -u -r1.42 -r1.42.8.1 src/sys/dev/mii/makphy.c
cvs rdiff -u -r1.6 -r1.6.20.1 src/sys/dev/mii/makphyreg.h
cvs rdiff -u -r1.125.6.3 -r1.125.6.4 src/sys/dev/mii/miidevs
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/mii/makphy.c
diff -u src/sys/dev/mii/makphy.c:1.42 src/sys/dev/mii/makphy.c:1.42.8.1
--- src/sys/dev/mii/makphy.c:1.42 Tue Nov 8 08:48:35 2016
+++ src/sys/dev/mii/makphy.c Thu Jan 17 17:23:02 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: makphy.c,v 1.42 2016/11/08 08:48:35 msaitoh Exp $ */
+/* $NetBSD: makphy.c,v 1.42.8.1 2019/01/17 17:23:02 martin Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
@@ -59,7 +59,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: makphy.c,v 1.42 2016/11/08 08:48:35 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: makphy.c,v 1.42.8.1 2019/01/17 17:23:02 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -92,44 +92,79 @@ static const struct mii_phy_funcs makphy
};
static const struct mii_phydesc makphys[] = {
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_0,
+ MII_STR_MARVELL_E1000_0 },
+
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_3,
+ MII_STR_MARVELL_E1000_3 },
+
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_5,
+ MII_STR_MARVELL_E1000_5 },
+
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_6,
+ MII_STR_MARVELL_E1000_6 },
+
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_3,
MII_STR_xxMARVELL_E1000_3 },
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_5,
MII_STR_xxMARVELL_E1000_5 },
+ { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000S,
+ MII_STR_xxMARVELL_E1000S },
+
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1011,
MII_STR_xxMARVELL_E1011 },
- /* XXX: reported not to work on eg. HP XW9400 */
- { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1149,
- MII_STR_xxMARVELL_E1149 },
-
- { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1149R,
- MII_STR_xxMARVELL_E1149R },
-
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1111,
MII_STR_xxMARVELL_E1111 },
+ { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1112,
+ MII_STR_xxMARVELL_E1112 },
+
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116,
MII_STR_xxMARVELL_E1116 },
- { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1145,
- MII_STR_xxMARVELL_E1145 },
-
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116R,
MII_STR_xxMARVELL_E1116R },
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116R_29,
MII_STR_xxMARVELL_E1116R_29 },
+ { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1118,
+ MII_STR_xxMARVELL_E1118 },
+
+ { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1145,
+ MII_STR_xxMARVELL_E1145 },
+
+ { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1149,
+ MII_STR_xxMARVELL_E1149 },
+
+ { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1149R,
+ MII_STR_xxMARVELL_E1149R },
+
+ { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1512,
+ MII_STR_xxMARVELL_E1512 },
+
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1543,
MII_STR_xxMARVELL_E1543 },
+ { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E3016,
+ MII_STR_xxMARVELL_E3016 },
+
+ { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E3082,
+ MII_STR_xxMARVELL_E3082 },
+
+ { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_PHYG65G,
+ MII_STR_xxMARVELL_PHYG65G },
+
{ 0, 0,
NULL },
};
+#define MAKARG_PDOWN true /* Power DOWN */
+#define MAKARG_PUP false /* Power UP */
+
static int
makphymatch(device_t parent, cfdata_t match, void *aux)
{
@@ -164,26 +199,14 @@ makphyattach(device_t parent, device_t s
sc->mii_flags = ma->mii_flags;
sc->mii_anegticks = MII_ANEGTICKS;
+ /* Make sure page 0 is selected. */
+ PHY_WRITE(sc, MAKPHY_EADR, 0);
+
switch (sc->mii_mpd_model) {
case MII_MODEL_xxMARVELL_E1011:
case MII_MODEL_xxMARVELL_E1112:
- if (PHY_READ(sc, MII_MAKPHY_ESSR) & ESSR_FIBER_LINK)
+ if (PHY_READ(sc, MAKPHY_ESSR) & ESSR_FIBER_LINK)
sc->mii_flags |= MIIF_HAVEFIBER;
- break;
- case MII_MODEL_xxMARVELL_E1149:
- case MII_MODEL_xxMARVELL_E1149R:
- /*
- * Some 88E1149 PHY's page select is initialized to
- * point to other bank instead of copper/fiber bank
- * which in turn resulted in wrong registers were
- * accessed during PHY operation. It is believed that
- * page 0 should be used for copper PHY so reinitialize
- * MII_MAKPHY_EADR to select default copper PHY. If parent
- * device know the type of PHY(either copper or fiber),
- * that information should be used to select default
- * type of PHY.
- */
- PHY_WRITE(sc, MII_MAKPHY_EADR, 0);
break;
default:
break;
@@ -207,20 +230,85 @@ makphyattach(device_t parent, device_t s
static void
makphy_reset(struct mii_softc *sc)
{
- uint16_t pscr;
+ uint16_t reg;
+
+ mii_phy_reset(sc);
+
+ /*
+ * Initialize PHY Specific Control Register.
+ */
+ reg = PHY_READ(sc, MAKPHY_PSCR);
+
+ /* Assert CRS on transmit. */
+ switch (sc->mii_mpd_model) {
+ case MII_MODEL_MARVELL_E1000_0:
+ case MII_MODEL_MARVELL_E1000_3:
+ case MII_MODEL_MARVELL_E1000_5:
+ case MII_MODEL_MARVELL_E1000_6:
+ case MII_MODEL_xxMARVELL_E1000S:
+ case MII_MODEL_xxMARVELL_E1011:
+ case MII_MODEL_xxMARVELL_E1111:
+ reg |= PSCR_CRS_ON_TX;
+ break;
+ default: /* No PSCR_CRS_ON_TX bit */
+ break;
+ }
- /* Assert CRS on transmit */
- pscr = PHY_READ(sc, MII_MAKPHY_PSCR);
- PHY_WRITE(sc, MII_MAKPHY_PSCR, pscr | PSCR_CRS_ON_TX);
+ /* Enable scrambler if necessary. */
+ if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E3016)
+ reg &= ~E3016_PSCR_SCRAMBLE_DIS;
+
+ /*
+ * Store next page in the Link Partner Next Page register for
+ * compatibility with 802.3ab.
+ */
+ if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E3016)
+ reg |= E3016_PSCR_REG8NXTPG;
+
+ PHY_WRITE(sc, MAKPHY_PSCR, reg);
+
+ /* Configure LEDs if they were left unconfigured. */
+ if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E3016 &&
+ PHY_READ(sc, 0x16) == 0) {
+ reg = (0x0b << 8) | (0x05 << 4) | 0x04; /* XXX */
+ PHY_WRITE(sc, 0x16, reg);
+ }
mii_phy_reset(sc);
}
+static void
+makphy_pdown(struct mii_softc *sc, bool pdown)
+{
+ int bmcr, new;
+ bool need_reset = false;
+
+ /*
+ * XXX
+ * PSCR (register 16) should be modified on some chips.
+ */
+
+ bmcr = PHY_READ(sc, MII_BMCR);
+ if (pdown)
+ new = bmcr | BMCR_PDOWN;
+ else
+ new = bmcr & ~BMCR_PDOWN;
+ if (bmcr != new)
+ need_reset = true;
+
+ if (need_reset)
+ new |= BMCR_RESET;
+ PHY_WRITE(sc, MII_BMCR, new);
+}
+
static int
makphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
{
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
- int reg;
+ int bmcr;
+
+ if (!device_is_active(sc->mii_dev))
+ return (ENXIO);
switch (cmd) {
case MII_POLLSTAT:
@@ -237,8 +325,8 @@ makphy_service(struct mii_softc *sc, str
* isolate ourselves.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
- reg = PHY_READ(sc, MII_BMCR);
- PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
+ bmcr = PHY_READ(sc, MII_BMCR);
+ PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
return (0);
}
@@ -248,15 +336,21 @@ makphy_service(struct mii_softc *sc, str
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
+ /* Try to power up the PHY in case it's down */
+ if (IFM_SUBTYPE(ife->ifm_media) != IFM_NONE)
+ makphy_pdown(sc, MAKARG_PUP);
+
mii_phy_setmedia(sc);
- if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
- /*
- * when not in auto mode, we need to restart nego
- * anyway, or a switch from a fixed mode to another
- * fixed mode may not be seen by the switch.
- */
- PHY_WRITE(sc, MII_BMCR,
- PHY_READ(sc, MII_BMCR) | BMCR_STARTNEG);
+
+ /*
+ * If autonegitation is not enabled, we need a
+ * software reset for the settings to take effect.
+ */
+ if (IFM_SUBTYPE(ife->ifm_media) == IFM_NONE)
+ makphy_pdown(sc, MAKARG_PDOWN);
+ else if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
+ bmcr = PHY_READ(sc, MII_BMCR);
+ PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET);
}
break;
@@ -288,65 +382,73 @@ static void
makphy_status(struct mii_softc *sc)
{
struct mii_data *mii = sc->mii_pdata;
- struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
- int bmcr, pssr, gtsr;
+ int bmcr, gsr, pssr;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
- pssr = PHY_READ(sc, MII_MAKPHY_PSSR);
+ bmcr = PHY_READ(sc, MII_BMCR);
+ /* XXX FIXME: Use different page for Fiber on newer chips */
+ pssr = PHY_READ(sc, MAKPHY_PSSR);
if (pssr & PSSR_LINK)
mii->mii_media_status |= IFM_ACTIVE;
- bmcr = PHY_READ(sc, MII_BMCR);
+ if (bmcr & BMCR_LOOP)
+ mii->mii_media_active |= IFM_LOOP;
+
if (bmcr & BMCR_ISO) {
mii->mii_media_active |= IFM_NONE;
mii->mii_media_status = 0;
return;
}
- if (bmcr & BMCR_LOOP)
- mii->mii_media_active |= IFM_LOOP;
-
- if (bmcr & BMCR_AUTOEN) {
+ if ((bmcr & BMCR_AUTOEN) != 0) {
/*
- * The media status bits are only valid of autonegotiation
- * has completed (or it's disabled).
+ * Check Speed and Duplex Resolved bit.
+ * Note that this bit is always 1 when autonego is not enabled.
*/
- if ((pssr & PSSR_RESOLVED) == 0) {
+ if (!(pssr & PSSR_RESOLVED)) {
/* Erg, still trying, I guess... */
mii->mii_media_active |= IFM_NONE;
return;
}
+ } else {
+ if ((pssr & PSSR_LINK) == 0) {
+ mii->mii_media_active |= IFM_NONE;
+ return;
+ }
+ }
+ /* XXX FIXME: Use different page for Fiber on newer chips */
+ if (sc->mii_flags & MIIF_IS_1000X) {
+ mii->mii_media_active |= IFM_1000_SX;
+ } else {
switch (PSSR_SPEED_get(pssr)) {
case SPEED_1000:
mii->mii_media_active |= IFM_1000_T;
- gtsr = PHY_READ(sc, MII_100T2SR);
- if (gtsr & GTSR_MS_RES)
- mii->mii_media_active |= IFM_ETH_MASTER;
break;
-
case SPEED_100:
mii->mii_media_active |= IFM_100_TX;
break;
-
case SPEED_10:
mii->mii_media_active |= IFM_10_T;
break;
-
- default:
+ default: /* Undefined (reserved) value */
mii->mii_media_active |= IFM_NONE;
mii->mii_media_status = 0;
return;
}
+ }
+
+ if (pssr & PSSR_DUPLEX)
+ mii->mii_media_active |= mii_phy_flowstatus(sc) | IFM_FDX;
+ else
+ mii->mii_media_active |= IFM_HDX;
- if (pssr & PSSR_DUPLEX)
- mii->mii_media_active |=
- IFM_FDX | mii_phy_flowstatus(sc);
- else
- mii->mii_media_active |= IFM_HDX;
- } else
- mii->mii_media_active = ife->ifm_media;
+ if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
+ gsr = PHY_READ(sc, MII_100T2SR);
+ if (gsr & GTSR_MS_RES)
+ mii->mii_media_active |= IFM_ETH_MASTER;
+ }
}
Index: src/sys/dev/mii/makphyreg.h
diff -u src/sys/dev/mii/makphyreg.h:1.6 src/sys/dev/mii/makphyreg.h:1.6.20.1
--- src/sys/dev/mii/makphyreg.h:1.6 Tue May 13 02:53:54 2014
+++ src/sys/dev/mii/makphyreg.h Thu Jan 17 17:23:02 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: makphyreg.h,v 1.6 2014/05/13 02:53:54 christos Exp $ */
+/* $NetBSD: makphyreg.h,v 1.6.20.1 2019/01/17 17:23:02 martin Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -36,7 +36,7 @@
* Marvell 88E1000 ``Alaska'' 10/100/1000 PHY registers.
*/
-#define MII_MAKPHY_PSCR 0x10 /* PHY specific control register */
+#define MAKPHY_PSCR 0x10 /* PHY specific control register */
#define PSCR_DIS_JABBER (1U << 0) /* disable jabber */
#define PSCR_POL_REV (1U << 1) /* polarity reversal */
#define PSCR_SQE_TEST (1U << 2) /* SQE test */
@@ -44,6 +44,7 @@
#define PSCR_DIS_125CLK (1U << 4) /* 125CLK low */
#define PSCR_MDI_XOVER_MODE(x) ((x) << 5) /* crossover mode */
#define PSCR_LOW_10T_THRESH (1U << 7) /* lower 10BASE-T Rx threshold */
+#define PSCR_EN_DETECT(x) ((x) << 8) /* Energy Detect */
#define PSCR_FORCE_LINK_GOOD (1U << 10) /* force link good */
#define PSCR_CRS_ON_TX (1U << 11) /* assert CRS on transmit */
#define PSCR_RX_FIFO(x) ((x) << 12) /* Rx FIFO depth */
@@ -53,7 +54,44 @@
#define XOVER_MODE_MDIX 1
#define XOVER_MODE_AUTO 2
-#define MII_MAKPHY_PSSR 0x11 /* PHY specific status register */
+/* 88E3016 */
+/* bit 2 and 3 are reserved */
+#define E3016_PSCR_MDI_XOVER_MODE(x) ((x) << 4) /* crossover mode */
+#define E3016_PSCR_SIGDET_POLARITY (1U << 6) /* 0: Active H, 1: Active L */
+#define E3016_PSCR_EXTDIST (1U << 7) /* Enable Extended Distance */
+#define E3016_PSCR_FEFI_DIS (1U << 8) /* Disable FEFI */
+#define E3016_PSCR_SCRAMBLE_DIS (1U << 9) /* Disable Scrambler */
+/* bit 10 is reserved */
+#define E3016_PSCR_NLPGEN_DIS (1U << 11) /* Disable Linkpulse Generation */
+#define E3016_PSCR_REG8NXTPG (1U << 12) /* En. Link Partner Next Page R */
+#define E3016_PSCR_NLPCHK_DIS (1U << 13) /* Disable NLP check */
+#define E3016_PSCR_EN_DETECT (1U << 14) /* Energy Detect */
+/* bit 15 is reserved */
+
+/* 88E1112 page 1 */
+#define MAKPHY_FSCR 0x10 /* Fiber specific control register */
+#define FSCR_XMITTER_DIS 0x0008 /* Transmitter Disable */
+
+/* 88E1112 page 2 */
+#define MAKPHY_MSCR 0x10 /* MAC specific control register */
+#define MSCR_TX_FIFODEPTH 0xc000 /* Transmi FIFO Depth */
+#define MSCR_RX_FIFODEPTH 0x3000 /* Receive FIFO Depth */
+#define MSCR_AUTOPREF_MASK 0x0c00 /* Autoselect preferred media mask */
+#define MSCR_AUTOPREF_NO 0x0000 /* No preference */
+#define MSCR_AUTOPREF_FIBER 0x0400 /* Preferred Fiber */
+#define MSCR_AUTOPREF_COPPER 0x0800 /* Preferred Copper */
+#define MSCR_MODE_MASK 0x0380 /* Mode select mask */
+#define MSCR_M_100FX 0x0000 /* 100BASE-FX */
+#define MSCR_M_COOPER_GBIC 0x0080 /* Copper GBIC */
+#define MSCR_M_AUTO_COPPER_SGMII 0x0100 /* Auto Copper/SGMII */
+#define MSCR_M_AUTO_COPPER_1000X 0x0180 /* Auto Copper/1000BASE-X */
+#define MSCR_M_COPPER 0x0280 /* Copper only */
+#define MSCR_M_SGMII 0x0300 /* SGMII only */
+#define MSCR_M_1000X 0x0380 /* 1000BASE-X only */
+#define MSCR_SGMII_PDOWN 0x0008 /* SGMII MAC Interface Power Down */
+#define MSCR_ENHANCED_SGMII 0x0004 /* Enhanced SGMII */
+
+#define MAKPHY_PSSR 0x11 /* PHY specific status register */
#define PSSR_JABBER (1U << 0) /* jabber indication */
#define PSSR_POLARITY (1U << 1) /* polarity indiciation */
#define PSSR_MDIX (1U << 6) /* 1 = MIDX, 0 = MDI */
@@ -69,7 +107,7 @@
#define SPEED_1000 2
#define SPEED_reserved 3
-#define MII_MAKPHY_IE 0x12 /* Interrupt enable */
+#define MAKPHY_IE 0x12 /* Interrupt enable */
#define IE_JABBER (1U << 0) /* jabber indication */
#define IE_POL_CHANGED (1U << 1) /* polarity changed */
#define IE_MDI_XOVER_CHANGED (1U << 6) /* MDI/MDIX changed */
@@ -83,20 +121,20 @@
#define IE_SPEED_CHANGED (1U << 14) /* speed changed */
#define IE_ANEG_ERROR (1U << 15) /* autonegotiation error occurred */
-#define MII_MAKPHY_IS 0x13 /* Interrupt status */
+#define MAKPHY_IS 0x13 /* Interrupt status */
/* See Interrupt enable bits */
-#define MII_MAKPHY_EPSC 0x14 /* extended PHY specific control */
+#define MAKPHY_EPSC 0x14 /* extended PHY specific control */
#define EPSC_TX_CLK(x) ((x) << 4) /* transmit clock */
#define EPSC_TBI_RCLK_DIS (1U << 12) /* TBI RCLK disable */
#define EPSC_TBI_RX_CLK125_EN (1U << 13) /* TBI RX_CLK125 enable */
#define EPSC_LINK_DOWN_NO_IDLES (1U << 15) /* 1 = lost lock detect */
-#define MII_MAKPHY_REC 0x15 /* receive error counter */
+#define MAKPHY_REC 0x15 /* receive error counter */
-#define MII_MAKPHY_EADR 0x16 /* extended address register */
+#define MAKPHY_EADR 0x16 /* extended address register */
-#define MII_MAKPHY_LEDCTRL 0x18 /* LED control */
+#define MAKPHY_LEDCTRL 0x18 /* LED control */
#define LEDCTRL_LED_TX (1U << 0) /* 1 = activ/link, 0 = xmit */
#define LEDCTRL_LED_RX (1U << 1) /* 1 = activ/link, 1 = recv */
#define LEDCTRL_LED_DUPLEX (1U << 2) /* 1 = duplex, 0 = dup/coll */
@@ -105,10 +143,21 @@
#define LEDCTRL_PULSE_STRCH(x) ((x) << 12)
#define LEDCTRL_DISABLE (1U << 15) /* disable LED */
-#define MII_MAKPHY_ESSR 0x1b /* Extended PHY specific status */
-#define ESSR_FIBER_LINK 0x2000
+#define MAKPHY_ESSR 0x1b /* Extended PHY specific status */
+#define ESSR_AUTOSEL_DISABLE 0x8000 /* Fiber/Copper autoselect disable */
+#define ESSR_FIBER_LINK 0x2000 /* Fiber/Copper resolution */
+#define ESSR_SER_ANEG_BYPASS 0x1000 /* Serial Iface Aneg bypass enable */
+#define ESSR_SER_ANEG_BYPASS_ST 0x0800 /* Serial Iface Aneg bypass status */
+#define ESSR_INTR_POLARITY 0x0400 /* Interrupt Polarity */
+#define ESSR_AUTO_MEDIAREG_SEL 0x0200 /* Auto Medium Register Selection */
+#define ESSR_DTE_DROP_HYST 0x01e0 /* DTE detect status drop hysteresis */
+#define ESSR_DTE_POWER 0x0010
+#define ESSR_HWCFG_MODE 0x000f
#define ESSR_GMII_COPPER 0x000f
#define ESSR_GMII_FIBER 0x0007
+#define ESSR_RGMII_COPPER 0x000b
+#define ESSR_RGMII_FIBER 0x0003
+#define ESSR_RGMII_SGMII 0x0006
#define ESSR_TBI_COPPER 0x000d
#define ESSR_TBI_FIBER 0x0005
Index: src/sys/dev/mii/miidevs
diff -u src/sys/dev/mii/miidevs:1.125.6.3 src/sys/dev/mii/miidevs:1.125.6.4
--- src/sys/dev/mii/miidevs:1.125.6.3 Tue Dec 4 11:15:20 2018
+++ src/sys/dev/mii/miidevs Thu Jan 17 17:23:02 2019
@@ -1,4 +1,4 @@
-$NetBSD: miidevs,v 1.125.6.3 2018/12/04 11:15:20 martin Exp $
+$NetBSD: miidevs,v 1.125.6.4 2019/01/17 17:23:02 martin Exp $
/*-
* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
@@ -282,11 +282,12 @@ model xxMARVELL E1149R 0x0025 Marvell 8
model xxMARVELL E3016 0x0026 Marvell 88E3016 10/100 Fast Ethernet PHY
model xxMARVELL PHYG65G 0x0027 Marvell PHYG65G Gigabit PHY
model xxMARVELL E1116R_29 0x0029 Marvell 88E1116R Gigabit PHY
-model xxMARVELL E1543 0x002a Marvell 88E1543 Alaska Quad Port Gb PHY
-model MARVELL E1000 0x0000 Marvell 88E1000 Gigabit PHY
+model xxMARVELL E1543 0x002a Marvell 88E154[358] Alaska Quad Port Gb PHY
+model MARVELL E1000_0 0x0000 Marvell 88E1000 Gigabit PHY
model MARVELL E1011 0x0002 Marvell 88E1011 Gigabit PHY
model MARVELL E1000_3 0x0003 Marvell 88E1000 Gigabit PHY
model MARVELL E1000_5 0x0005 Marvell 88E1000 Gigabit PHY
+model MARVELL E1000_6 0x0006 Marvell 88E1000 Gigabit PHY
model MARVELL E1111 0x000c Marvell 88E1111 Gigabit PHY
/* Micrel PHYs */
