Module Name: src
Committed By: martin
Date: Thu Mar 7 17:17:09 UTC 2019
Modified Files:
src/sys/dev/mii [netbsd-8]: miidevs.h miidevs_data.h
Log Message:
Regen for ticket #1207
To generate a diff of this commit:
cvs rdiff -u -r1.128.6.4 -r1.128.6.5 src/sys/dev/mii/miidevs.h
cvs rdiff -u -r1.116.6.4 -r1.116.6.5 src/sys/dev/mii/miidevs_data.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/mii/miidevs.h
diff -u src/sys/dev/mii/miidevs.h:1.128.6.4 src/sys/dev/mii/miidevs.h:1.128.6.5
--- src/sys/dev/mii/miidevs.h:1.128.6.4 Thu Jan 17 17:23:36 2019
+++ src/sys/dev/mii/miidevs.h Thu Mar 7 17:17:09 2019
@@ -1,10 +1,10 @@
-/* $NetBSD: miidevs.h,v 1.128.6.4 2019/01/17 17:23:36 martin Exp $ */
+/* $NetBSD: miidevs.h,v 1.128.6.5 2019/03/07 17:17:09 martin Exp $ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD: miidevs,v 1.125.6.4 2019/01/17 17:23:02 martin Exp
+ * NetBSD: miidevs,v 1.125.6.5 2019/03/07 17:16:40 martin Exp
*/
/*-
@@ -57,16 +57,25 @@
*/
#define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */
+#define MII_OUI_VITESSE 0x0001c1 /* Vitesse */
+#define MII_OUI_TRIDIUM 0x0001f0 /* Tridium */
+#define MII_OUI_DATATRACK 0x0002c6 /* Data Track Technology */
#define MII_OUI_CICADA 0x0003f1 /* Cicada Semiconductor */
#define MII_OUI_AGERE 0x00053d /* Agere */
+#define MII_OUI_NETAS 0x0009c3 /* Netas */
#define MII_OUI_BROADCOM2 0x000af7 /* Broadcom Corporation */
+#define MII_OUI_RALINK 0x000c43 /* Ralink Technology */
+#define MII_OUI_ASIX 0x000ec6 /* ASIX */
#define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */
#define MII_OUI_MICREL 0x0010a1 /* Micrel */
#define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */
#define MII_OUI_ENABLESEMI 0x0010dd /* Enable Semiconductor */
+#define MII_OUI_SUNPLUS 0x001105 /* Sunplus Technology */
#define MII_OUI_ATHEROS 0x001374 /* Atheros */
+#define MII_OUI_RALINK2 0x0017a5 /* Ralink Technology */
#define MII_OUI_BROADCOM3 0x001be9 /* Broadcom Corporation */
#define MII_OUI_LEVEL1 0x00207b /* Level 1 */
+#define MII_OUI_VIA 0x004063 /* VIA Technologies */
#define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */
#define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */
#define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */
@@ -83,9 +92,11 @@
#define MII_OUI_PMCSIERRA 0x00e004 /* PMC-Sierra */
#define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */
#define MII_OUI_REALTEK 0x00e04c /* RealTek */
+#define MII_OUI_ADMTEK 0x00e092 /* ADMtek */
#define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */
#define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */
#define MII_OUI_TI 0x080028 /* Texas Instruments */
+#define MII_OUI_BROADCOM4 0x18c086 /* Broadcom Corporation */
/* Some Intel 82553's use an alternative OUI. */
#define MII_OUI_xxINTEL 0x001f00 /* Intel */
@@ -130,6 +141,20 @@
#define MII_MODEL_xxASIX_AX88X9X 0x0031
#define MII_STR_xxASIX_AX88X9X "Ax88x9x internal PHY"
+/* Altima Communications PHYs */
+/* Don't know the model for ACXXX */
+#define MII_MODEL_ALTIMA_ACXXX 0x0001
+#define MII_STR_ALTIMA_ACXXX "ACXXX 10/100 media interface"
+#define MII_MODEL_ALTIMA_AC101L 0x0012
+#define MII_STR_ALTIMA_AC101L "AC101L 10/100 media interface"
+#define MII_MODEL_ALTIMA_AC101 0x0021
+#define MII_STR_ALTIMA_AC101 "AC101 10/100 media interface"
+/* AMD Am79C87[45] have ALTIMA OUI */
+#define MII_MODEL_ALTIMA_Am79C875 0x0014
+#define MII_STR_ALTIMA_Am79C875 "Am79C875 10/100 media interface"
+#define MII_MODEL_ALTIMA_Am79C874 0x0021
+#define MII_STR_ALTIMA_Am79C874 "Am79C874 10/100 media interface"
+
/* Atheros PHYs */
#define MII_MODEL_ATHEROS_F1 0x0001
#define MII_STR_ATHEROS_F1 "F1 10/100/1000 PHY"
@@ -146,20 +171,6 @@
#define MII_MODEL_ATTANSIC_AR8035 0x0007
#define MII_STR_ATTANSIC_AR8035 "Atheros AR8035 10/100/1000 PHY"
-/* Altima Communications PHYs */
-/* Don't know the model for ACXXX */
-#define MII_MODEL_ALTIMA_ACXXX 0x0001
-#define MII_STR_ALTIMA_ACXXX "ACXXX 10/100 media interface"
-#define MII_MODEL_ALTIMA_AC101 0x0021
-#define MII_STR_ALTIMA_AC101 "AC101 10/100 media interface"
-#define MII_MODEL_ALTIMA_AC101L 0x0012
-#define MII_STR_ALTIMA_AC101L "AC101L 10/100 media interface"
-/* AMD Am79C87[45] have ALTIMA OUI */
-#define MII_MODEL_ALTIMA_Am79C875 0x0014
-#define MII_STR_ALTIMA_Am79C875 "Am79C875 10/100 media interface"
-#define MII_MODEL_ALTIMA_Am79C874 0x0021
-#define MII_STR_ALTIMA_Am79C874 "Am79C874 10/100 media interface"
-
/* Advanced Micro Devices PHYs */
/* see Davicom DM9101 for Am79C873 */
#define MII_MODEL_yyAMD_79C972_10T 0x0001
@@ -176,12 +187,12 @@
#define MII_STR_xxBROADCOM_3C905B "Broadcom 3c905B internal PHY"
#define MII_MODEL_xxBROADCOM_3C905C 0x0017
#define MII_STR_xxBROADCOM_3C905C "Broadcom 3c905C internal PHY"
+#define MII_MODEL_xxBROADCOM_BCM5221 0x001e
+#define MII_STR_xxBROADCOM_BCM5221 "BCM5221 10/100 media interface"
#define MII_MODEL_xxBROADCOM_BCM5201 0x0021
#define MII_STR_xxBROADCOM_BCM5201 "BCM5201 10/100 media interface"
#define MII_MODEL_xxBROADCOM_BCM5214 0x0028
#define MII_STR_xxBROADCOM_BCM5214 "BCM5214 Quad 10/100 media interface"
-#define MII_MODEL_xxBROADCOM_BCM5221 0x001e
-#define MII_STR_xxBROADCOM_BCM5221 "BCM5221 10/100 media interface"
#define MII_MODEL_xxBROADCOM_BCM5222 0x0032
#define MII_STR_xxBROADCOM_BCM5222 "BCM5222 Dual 10/100 media interface"
#define MII_MODEL_xxBROADCOM_BCM4401 0x0036
@@ -192,8 +203,14 @@
#define MII_STR_BROADCOM_BCM5400 "BCM5400 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5401 0x0005
#define MII_STR_BROADCOM_BCM5401 "BCM5401 1000BASE-T media interface"
+#define MII_MODEL_BROADCOM_BCM5402 0x0006
+#define MII_STR_BROADCOM_BCM5402 "BCM5402 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5411 0x0007
#define MII_STR_BROADCOM_BCM5411 "BCM5411 1000BASE-T media interface"
+#define MII_MODEL_BROADCOM_BCM5404 0x0008
+#define MII_STR_BROADCOM_BCM5404 "BCM5404 1000BASE-T media interface"
+#define MII_MODEL_BROADCOM_BCM5424 0x000a
+#define MII_STR_BROADCOM_BCM5424 "BCM5424/BCM5234 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5464 0x000b
#define MII_STR_BROADCOM_BCM5464 "BCM5464 1000BASE-T media interface"
#define MII_MODEL_BROADCOM_BCM5461 0x000c
@@ -224,10 +241,16 @@
#define MII_STR_BROADCOM_BCM5780 "BCM5780 1000BASE-T/X media interface"
#define MII_MODEL_BROADCOM_BCM5708C 0x0036
#define MII_STR_BROADCOM_BCM5708C "BCM5708C 1000BASE-T media interface"
+#define MII_MODEL_BROADCOM_BCM5466 0x003b
+#define MII_STR_BROADCOM_BCM5466 "BCM5466 1000BASE-T media interface"
#define MII_MODEL_BROADCOM2_BCM5325 0x0003
#define MII_STR_BROADCOM2_BCM5325 "BCM5325 10/100 5-port PHY switch"
#define MII_MODEL_BROADCOM2_BCM5906 0x0004
#define MII_STR_BROADCOM2_BCM5906 "BCM5906 10/100baseTX media interface"
+#define MII_MODEL_BROADCOM2_BCM5478 0x0008
+#define MII_STR_BROADCOM2_BCM5478 "BCM5478 1000BASE-T media interface"
+#define MII_MODEL_BROADCOM2_BCM5488 0x0009
+#define MII_STR_BROADCOM2_BCM5488 "BCM5488 1000BASE-T media interface"
#define MII_MODEL_BROADCOM2_BCM5481 0x000a
#define MII_STR_BROADCOM2_BCM5481 "BCM5481 1000BASE-T media interface"
#define MII_MODEL_BROADCOM2_BCM5482 0x000b
@@ -264,6 +287,8 @@
#define MII_STR_BROADCOM3_BCM57765 "BCM57765 1000BASE-T media interface"
#define MII_MODEL_BROADCOM3_BCM5720C 0x0036
#define MII_STR_BROADCOM3_BCM5720C "BCM5720C 1000BASE-T media interface"
+#define MII_MODEL_BROADCOM4_BCM5725C 0x0038
+#define MII_STR_BROADCOM4_BCM5725C "BCM5725C 1000BASE-T media interface"
#define MII_MODEL_xxBROADCOM_ALT1_BCM5906 0x0004
#define MII_STR_xxBROADCOM_ALT1_BCM5906 "BCM5906 10/100baseTX media interface"
@@ -278,15 +303,17 @@
#define MII_STR_CICADA_CS8201A "Cicada CS8201 10/100/1000TX PHY"
#define MII_MODEL_CICADA_CS8201B 0x0021
#define MII_STR_CICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY"
+#define MII_MODEL_CICADA_CS8244 0x002c
+#define MII_STR_CICADA_CS8244 "Vitesse VSC8244 Quad 10/100/1000BASE-T PHY"
#define MII_MODEL_xxCICADA_VSC8221 0x0015
#define MII_STR_xxCICADA_VSC8221 "Vitesse VSC8221 10/100/1000BASE-T PHY"
-#define MII_MODEL_xxCICADA_VSC8244 0x002c
-#define MII_STR_xxCICADA_VSC8244 "Vitesse VSC8244 Quad 10/100/1000BASE-T PHY"
#define MII_MODEL_xxCICADA_CS8201B 0x0021
#define MII_STR_xxCICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY"
/* Davicom Semiconductor PHYs */
/* AMD Am79C873 seems to be a relabeled DM9101 */
+#define MII_MODEL_DAVICOM_DM9101 0x0000
+#define MII_STR_DAVICOM_DM9101 "DM9101 (AMD Am79C873) 10/100 media interface"
#define MII_MODEL_xxDAVICOM_DM9101 0x0000
#define MII_STR_xxDAVICOM_DM9101 "DM9101 (AMD Am79C873) 10/100 media interface"
#define MII_MODEL_xxDAVICOM_DM9102 0x0004
@@ -311,6 +338,8 @@
#define MII_STR_ICS_1892 "ICS1892 10/100 media interface"
#define MII_MODEL_ICS_1893 0x0004
#define MII_STR_ICS_1893 "ICS1893 10/100 media interface"
+#define MII_MODEL_ICS_1893C 0x0005
+#define MII_STR_ICS_1893C "ICS1893C 10/100 media interface"
/* Intel PHYs */
#define MII_MODEL_xxINTEL_I82553 0x0000
@@ -364,18 +393,18 @@
/* Level 1 PHYs */
#define MII_MODEL_xxLEVEL1_LXT970 0x0000
#define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface"
-#define MII_MODEL_LEVEL1_LXT971 0x000e
-#define MII_STR_LEVEL1_LXT971 "LXT971/2 10/100 media interface"
-#define MII_MODEL_LEVEL1_LXT973 0x0021
-#define MII_STR_LEVEL1_LXT973 "LXT973 10/100 Dual PHY"
+#define MII_MODEL_LEVEL1_LXT1000_OLD 0x0003
+#define MII_STR_LEVEL1_LXT1000_OLD "LXT1000 1000BASE-T media interface"
#define MII_MODEL_LEVEL1_LXT974 0x0004
#define MII_STR_LEVEL1_LXT974 "LXT974 10/100 Quad PHY"
#define MII_MODEL_LEVEL1_LXT975 0x0005
#define MII_STR_LEVEL1_LXT975 "LXT975 10/100 Quad PHY"
-#define MII_MODEL_LEVEL1_LXT1000_OLD 0x0003
-#define MII_STR_LEVEL1_LXT1000_OLD "LXT1000 1000BASE-T media interface"
#define MII_MODEL_LEVEL1_LXT1000 0x000c
#define MII_STR_LEVEL1_LXT1000 "LXT1000 1000BASE-T media interface"
+#define MII_MODEL_LEVEL1_LXT971 0x000e
+#define MII_STR_LEVEL1_LXT971 "LXT971/2 10/100 media interface"
+#define MII_MODEL_LEVEL1_LXT973 0x0021
+#define MII_STR_LEVEL1_LXT973 "LXT973 10/100 Dual PHY"
/* Marvell Semiconductor PHYs */
#define MII_MODEL_xxMARVELL_E1000 0x0000
@@ -412,6 +441,8 @@
#define MII_STR_xxMARVELL_E1116 "Marvell 88E1116 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1118 0x0022
#define MII_STR_xxMARVELL_E1118 "Marvell 88E1118 Gigabit PHY"
+#define MII_MODEL_xxMARVELL_E1240 0x0023
+#define MII_STR_xxMARVELL_E1240 "Marvell 88E1240 Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1116R 0x0024
#define MII_STR_xxMARVELL_E1116R "Marvell 88E1116R Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1149R 0x0025
@@ -420,8 +451,8 @@
#define MII_STR_xxMARVELL_E3016 "Marvell 88E3016 10/100 Fast Ethernet PHY"
#define MII_MODEL_xxMARVELL_PHYG65G 0x0027
#define MII_STR_xxMARVELL_PHYG65G "Marvell PHYG65G Gigabit PHY"
-#define MII_MODEL_xxMARVELL_E1116R_29 0x0029
-#define MII_STR_xxMARVELL_E1116R_29 "Marvell 88E1116R Gigabit PHY"
+#define MII_MODEL_xxMARVELL_E1318S 0x0029
+#define MII_STR_xxMARVELL_E1318S "Marvell 88E1318S Gigabit PHY"
#define MII_MODEL_xxMARVELL_E1543 0x002a
#define MII_STR_xxMARVELL_E1543 "Marvell 88E154[358] Alaska Quad Port Gb PHY"
#define MII_MODEL_MARVELL_E1000_0 0x0000
@@ -438,8 +469,12 @@
#define MII_STR_MARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
/* Micrel PHYs */
+#define MII_MODEL_MICREL_KSZ8081 0x0016
+#define MII_STR_MICREL_KSZ8081 "Micrel KSZ8081 10/100 PHY"
#define MII_MODEL_MICREL_KSZ9021RNI 0x0021
#define MII_STR_MICREL_KSZ9021RNI "Micrel KSZ9021RNI 10/100/1000 PHY"
+#define MII_MODEL_MICREL_KSZ9031 0x0022
+#define MII_STR_MICREL_KSZ9031 "Micrel KSZ9031 10/100/1000 PHY"
/* Myson Technology PHYs */
#define MII_MODEL_xxMYSON_MTD972 0x0000
@@ -482,13 +517,16 @@
/* RDC Semiconductor PHYs */
#define MII_MODEL_RDC_R6040 0x0003
#define MII_STR_RDC_R6040 "R6040 10/100 media interface"
+
/* RealTek PHYs */
-#define MII_MODEL_yyREALTEK_RTL8201L 0x0020
-#define MII_STR_yyREALTEK_RTL8201L "RTL8201L 10/100 media interface"
#define MII_MODEL_xxREALTEK_RTL8169S 0x0011
#define MII_STR_xxREALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface"
+#define MII_MODEL_yyREALTEK_RTL8201L 0x0020
+#define MII_STR_yyREALTEK_RTL8201L "RTL8201L 10/100 media interface"
#define MII_MODEL_REALTEK_RTL8251 0x0000
#define MII_STR_REALTEK_RTL8251 "RTL8251 1000BASE-T media interface"
+#define MII_MODEL_REALTEK_RTL8201E 0x0008
+#define MII_STR_REALTEK_RTL8201E "RTL8201E 10/100 media interface"
#define MII_MODEL_REALTEK_RTL8169S 0x0011
#define MII_STR_REALTEK_RTL8169S "RTL8169S/8110S/8211 1000BASE-T media interface"
@@ -505,10 +543,18 @@
#define MII_STR_SIS_900 "SiS 900 10/100 media interface"
/* SMSC PHYs */
+#define MII_MODEL_SMSC_LAN83C185 0x000a
+#define MII_STR_SMSC_LAN83C185 "SMSC LAN83C185 10/100 PHY"
#define MII_MODEL_SMSC_LAN8700 0x000c
#define MII_STR_SMSC_LAN8700 "SMSC LAN8700 10/100 Ethernet Transceiver"
#define MII_MODEL_SMSC_LAN8710_LAN8720 0x000f
#define MII_STR_SMSC_LAN8710_LAN8720 "SMSC LAN8710/LAN8720 10/100 Ethernet Transceiver"
+#define MII_MODEL_SMSC_LAN8740 0x0011
+#define MII_STR_SMSC_LAN8740 "SMSC LAN8740 10/100 media interface"
+#define MII_MODEL_SMSC_LAN8741A 0x0012
+#define MII_STR_SMSC_LAN8741A "SMSC LAN8741A 10/100 media interface"
+#define MII_MODEL_SMSC_LAN8742 0x0013
+#define MII_STR_SMSC_LAN8742 "SMSC LAN8742 10/100 media interface"
/* Texas Instruments PHYs */
#define MII_MODEL_TI_TLAN10T 0x0001
@@ -524,6 +570,16 @@
#define MII_MODEL_xxTSC_78Q2121 0x0015
#define MII_STR_xxTSC_78Q2121 "78Q2121 100BASE-TX media interface"
+/* VIA Technologies PHYs */
+#define MII_MODEL_VIA_VT6103 0x0032
+#define MII_STR_VIA_VT6103 "VT6103 10/100 PHY"
+#define MII_MODEL_VIA_VT6103_2 0x0034
+#define MII_STR_VIA_VT6103_2 "VT6103 10/100 PHY"
+
+/* Vitesse PHYs */
+#define MII_MODEL_VITESSE_VSC8601 0x0002
+#define MII_STR_VITESSE_VSC8601 "VSC8601 10/100/1000 PHY"
+
/* XaQti Corp. PHYs */
#define MII_MODEL_xxXAQTI_XMACII 0x0000
#define MII_STR_xxXAQTI_XMACII "XaQti Corp. XMAC II gigabit interface"
Index: src/sys/dev/mii/miidevs_data.h
diff -u src/sys/dev/mii/miidevs_data.h:1.116.6.4 src/sys/dev/mii/miidevs_data.h:1.116.6.5
--- src/sys/dev/mii/miidevs_data.h:1.116.6.4 Thu Jan 17 17:23:36 2019
+++ src/sys/dev/mii/miidevs_data.h Thu Mar 7 17:17:09 2019
@@ -1,10 +1,10 @@
-/* $NetBSD: miidevs_data.h,v 1.116.6.4 2019/01/17 17:23:36 martin Exp $ */
+/* $NetBSD: miidevs_data.h,v 1.116.6.5 2019/03/07 17:17:09 martin Exp $ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD: miidevs,v 1.125.6.4 2019/01/17 17:23:02 martin Exp
+ * NetBSD: miidevs,v 1.125.6.5 2019/03/07 17:16:40 martin Exp
*/
/*-
@@ -39,32 +39,35 @@
struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_AGERE, MII_MODEL_AGERE_ET1011, MII_STR_AGERE_ET1011 },
{ MII_OUI_xxASIX, MII_MODEL_xxASIX_AX88X9X, MII_STR_xxASIX_AX88X9X },
+ { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_ACXXX, MII_STR_ALTIMA_ACXXX },
+ { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101L, MII_STR_ALTIMA_AC101L },
+ { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101, MII_STR_ALTIMA_AC101 },
+ { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C875, MII_STR_ALTIMA_Am79C875 },
+ { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C874, MII_STR_ALTIMA_Am79C874 },
{ MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1, MII_STR_ATHEROS_F1 },
{ MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F2, MII_STR_ATHEROS_F2 },
{ MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L1, MII_STR_ATTANSIC_L1 },
{ MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L2, MII_STR_ATTANSIC_L2 },
{ MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8021, MII_STR_ATTANSIC_AR8021 },
{ MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8035, MII_STR_ATTANSIC_AR8035 },
- { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_ACXXX, MII_STR_ALTIMA_ACXXX },
- { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101, MII_STR_ALTIMA_AC101 },
- { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_AC101L, MII_STR_ALTIMA_AC101L },
- { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C875, MII_STR_ALTIMA_Am79C875 },
- { MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C874, MII_STR_ALTIMA_Am79C874 },
{ MII_OUI_yyAMD, MII_MODEL_yyAMD_79C972_10T, MII_STR_yyAMD_79C972_10T },
{ MII_OUI_yyAMD, MII_MODEL_yyAMD_79c973phy, MII_STR_yyAMD_79c973phy },
{ MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901, MII_STR_yyAMD_79c901 },
{ MII_OUI_yyAMD, MII_MODEL_yyAMD_79c901home, MII_STR_yyAMD_79c901home },
{ MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905B, MII_STR_xxBROADCOM_3C905B },
{ MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_3C905C, MII_STR_xxBROADCOM_3C905C },
+ { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5221, MII_STR_xxBROADCOM_BCM5221 },
{ MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5201, MII_STR_xxBROADCOM_BCM5201 },
{ MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5214, MII_STR_xxBROADCOM_BCM5214 },
- { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5221, MII_STR_xxBROADCOM_BCM5221 },
{ MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5222, MII_STR_xxBROADCOM_BCM5222 },
{ MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM4401, MII_STR_xxBROADCOM_BCM4401 },
{ MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5365, MII_STR_xxBROADCOM_BCM5365 },
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, MII_STR_BROADCOM_BCM5400 },
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, MII_STR_BROADCOM_BCM5401 },
+ { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5402, MII_STR_BROADCOM_BCM5402 },
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, MII_STR_BROADCOM_BCM5411 },
+ { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5404, MII_STR_BROADCOM_BCM5404 },
+ { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5424, MII_STR_BROADCOM_BCM5424 },
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5464, MII_STR_BROADCOM_BCM5464 },
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5461, MII_STR_BROADCOM_BCM5461 },
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, MII_STR_BROADCOM_BCM5462 },
@@ -80,8 +83,11 @@ struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, MII_STR_BROADCOM_BCM5714 },
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, MII_STR_BROADCOM_BCM5780 },
{ MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, MII_STR_BROADCOM_BCM5708C },
+ { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5466, MII_STR_BROADCOM_BCM5466 },
{ MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5325, MII_STR_BROADCOM2_BCM5325 },
{ MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5906, MII_STR_BROADCOM2_BCM5906 },
+ { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5478, MII_STR_BROADCOM2_BCM5478 },
+ { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5488, MII_STR_BROADCOM2_BCM5488 },
{ MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5481, MII_STR_BROADCOM2_BCM5481 },
{ MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5482, MII_STR_BROADCOM2_BCM5482 },
{ MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, MII_STR_BROADCOM2_BCM5755 },
@@ -100,15 +106,17 @@ struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5719C, MII_STR_BROADCOM3_BCM5719C },
{ MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57765, MII_STR_BROADCOM3_BCM57765 },
{ MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5720C, MII_STR_BROADCOM3_BCM5720C },
+ { MII_OUI_BROADCOM4, MII_MODEL_BROADCOM4_BCM5725C, MII_STR_BROADCOM4_BCM5725C },
{ MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, MII_STR_xxBROADCOM_ALT1_BCM5906 },
{ MII_OUI_CICADA, MII_MODEL_CICADA_CS8201, MII_STR_CICADA_CS8201 },
{ MII_OUI_CICADA, MII_MODEL_CICADA_CS8204, MII_STR_CICADA_CS8204 },
{ MII_OUI_CICADA, MII_MODEL_CICADA_VSC8211, MII_STR_CICADA_VSC8211 },
{ MII_OUI_CICADA, MII_MODEL_CICADA_CS8201A, MII_STR_CICADA_CS8201A },
{ MII_OUI_CICADA, MII_MODEL_CICADA_CS8201B, MII_STR_CICADA_CS8201B },
+ { MII_OUI_CICADA, MII_MODEL_CICADA_CS8244, MII_STR_CICADA_CS8244 },
{ MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8221, MII_STR_xxCICADA_VSC8221 },
- { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_VSC8244, MII_STR_xxCICADA_VSC8244 },
{ MII_OUI_xxCICADA, MII_MODEL_xxCICADA_CS8201B, MII_STR_xxCICADA_CS8201B },
+ { MII_OUI_DAVICOM, MII_MODEL_DAVICOM_DM9101, MII_STR_DAVICOM_DM9101 },
{ MII_OUI_xxDAVICOM, MII_MODEL_xxDAVICOM_DM9101, MII_STR_xxDAVICOM_DM9101 },
{ MII_OUI_xxDAVICOM, MII_MODEL_xxDAVICOM_DM9102, MII_STR_xxDAVICOM_DM9102 },
{ MII_OUI_ICPLUS, MII_MODEL_ICPLUS_IP100, MII_STR_ICPLUS_IP100 },
@@ -119,6 +127,7 @@ struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_ICS, MII_MODEL_ICS_1890, MII_STR_ICS_1890 },
{ MII_OUI_ICS, MII_MODEL_ICS_1892, MII_STR_ICS_1892 },
{ MII_OUI_ICS, MII_MODEL_ICS_1893, MII_STR_ICS_1893 },
+ { MII_OUI_ICS, MII_MODEL_ICS_1893C, MII_STR_ICS_1893C },
{ MII_OUI_xxINTEL, MII_MODEL_xxINTEL_I82553, MII_STR_xxINTEL_I82553 },
{ MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82555, MII_STR_yyINTEL_I82555 },
{ MII_OUI_yyINTEL, MII_MODEL_yyINTEL_I82562EH, MII_STR_yyINTEL_I82562EH },
@@ -142,12 +151,12 @@ struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_JMICRON, MII_MODEL_JMICRON_JMC250, MII_STR_JMICRON_JMC250 },
{ MII_OUI_JMICRON, MII_MODEL_JMICRON_JMC260, MII_STR_JMICRON_JMC260 },
{ MII_OUI_xxLEVEL1, MII_MODEL_xxLEVEL1_LXT970, MII_STR_xxLEVEL1_LXT970 },
- { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT971, MII_STR_LEVEL1_LXT971 },
- { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT973, MII_STR_LEVEL1_LXT973 },
+ { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT1000_OLD, MII_STR_LEVEL1_LXT1000_OLD },
{ MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT974, MII_STR_LEVEL1_LXT974 },
{ MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT975, MII_STR_LEVEL1_LXT975 },
- { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT1000_OLD, MII_STR_LEVEL1_LXT1000_OLD },
{ MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT1000, MII_STR_LEVEL1_LXT1000 },
+ { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT971, MII_STR_LEVEL1_LXT971 },
+ { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT973, MII_STR_LEVEL1_LXT973 },
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000, MII_STR_xxMARVELL_E1000 },
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1011, MII_STR_xxMARVELL_E1011 },
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_3, MII_STR_xxMARVELL_E1000_3 },
@@ -165,11 +174,12 @@ struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1340M, MII_STR_xxMARVELL_E1340M },
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116, MII_STR_xxMARVELL_E1116 },
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1118, MII_STR_xxMARVELL_E1118 },
+ { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1240, MII_STR_xxMARVELL_E1240 },
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116R, MII_STR_xxMARVELL_E1116R },
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1149R, MII_STR_xxMARVELL_E1149R },
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E3016, MII_STR_xxMARVELL_E3016 },
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_PHYG65G, MII_STR_xxMARVELL_PHYG65G },
- { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1116R_29, MII_STR_xxMARVELL_E1116R_29 },
+ { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1318S, MII_STR_xxMARVELL_E1318S },
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1543, MII_STR_xxMARVELL_E1543 },
{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_0, MII_STR_MARVELL_E1000_0 },
{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1011, MII_STR_MARVELL_E1011 },
@@ -177,7 +187,9 @@ struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_5, MII_STR_MARVELL_E1000_5 },
{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_6, MII_STR_MARVELL_E1000_6 },
{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1111, MII_STR_MARVELL_E1111 },
+ { MII_OUI_MICREL, MII_MODEL_MICREL_KSZ8081, MII_STR_MICREL_KSZ8081 },
{ MII_OUI_MICREL, MII_MODEL_MICREL_KSZ9021RNI, MII_STR_MICREL_KSZ9021RNI },
+ { MII_OUI_MICREL, MII_MODEL_MICREL_KSZ9031, MII_STR_MICREL_KSZ9031 },
{ MII_OUI_xxMYSON, MII_MODEL_xxMYSON_MTD972, MII_STR_xxMYSON_MTD972 },
{ MII_OUI_MYSON, MII_MODEL_MYSON_MTD803, MII_STR_MYSON_MTD803 },
{ MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83840, MII_STR_xxNATSEMI_DP83840 },
@@ -194,21 +206,29 @@ struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_PMCSIERRA, MII_MODEL_PMCSIERRA_PM8354, MII_STR_PMCSIERRA_PM8354 },
{ MII_OUI_xxQUALSEMI, MII_MODEL_xxQUALSEMI_QS6612, MII_STR_xxQUALSEMI_QS6612 },
{ MII_OUI_RDC, MII_MODEL_RDC_R6040, MII_STR_RDC_R6040 },
- { MII_OUI_yyREALTEK, MII_MODEL_yyREALTEK_RTL8201L, MII_STR_yyREALTEK_RTL8201L },
{ MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, MII_STR_xxREALTEK_RTL8169S },
+ { MII_OUI_yyREALTEK, MII_MODEL_yyREALTEK_RTL8201L, MII_STR_yyREALTEK_RTL8201L },
{ MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8251, MII_STR_REALTEK_RTL8251 },
+ { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8201E, MII_STR_REALTEK_RTL8201E },
{ MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, MII_STR_REALTEK_RTL8169S },
{ MII_OUI_SEEQ, MII_MODEL_SEEQ_80220, MII_STR_SEEQ_80220 },
{ MII_OUI_SEEQ, MII_MODEL_SEEQ_84220, MII_STR_SEEQ_84220 },
{ MII_OUI_SEEQ, MII_MODEL_SEEQ_80225, MII_STR_SEEQ_80225 },
{ MII_OUI_SIS, MII_MODEL_SIS_900, MII_STR_SIS_900 },
+ { MII_OUI_SMSC, MII_MODEL_SMSC_LAN83C185, MII_STR_SMSC_LAN83C185 },
{ MII_OUI_SMSC, MII_MODEL_SMSC_LAN8700, MII_STR_SMSC_LAN8700 },
{ MII_OUI_SMSC, MII_MODEL_SMSC_LAN8710_LAN8720, MII_STR_SMSC_LAN8710_LAN8720 },
+ { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8740, MII_STR_SMSC_LAN8740 },
+ { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8741A, MII_STR_SMSC_LAN8741A },
+ { MII_OUI_SMSC, MII_MODEL_SMSC_LAN8742, MII_STR_SMSC_LAN8742 },
{ MII_OUI_TI, MII_MODEL_TI_TLAN10T, MII_STR_TI_TLAN10T },
{ MII_OUI_TI, MII_MODEL_TI_100VGPMI, MII_STR_TI_100VGPMI },
{ MII_OUI_TI, MII_MODEL_TI_TNETE2101, MII_STR_TI_TNETE2101 },
{ MII_OUI_xxTSC, MII_MODEL_xxTSC_78Q2120, MII_STR_xxTSC_78Q2120 },
{ MII_OUI_xxTSC, MII_MODEL_xxTSC_78Q2121, MII_STR_xxTSC_78Q2121 },
+ { MII_OUI_VIA, MII_MODEL_VIA_VT6103, MII_STR_VIA_VT6103 },
+ { MII_OUI_VIA, MII_MODEL_VIA_VT6103_2, MII_STR_VIA_VT6103_2 },
+ { MII_OUI_VITESSE, MII_MODEL_VITESSE_VSC8601, MII_STR_VITESSE_VSC8601 },
{ MII_OUI_xxXAQTI, MII_MODEL_xxXAQTI_XMACII, MII_STR_xxXAQTI_XMACII },
{ 0, 0, NULL }
};
