Module Name: src
Committed By: jmcneill
Date: Sun Jan 20 17:28:00 UTC 2019
Modified Files:
src/sys/arch/arm/amlogic: meson_clk.h
Log Message:
Add CLK_SET_RATE_PARENT for mux clocks and add MESON_CLK_PLL_RATE which is like
MESON_CLK_PLL but accepts a custom set_rate function
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/amlogic/meson_clk.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/amlogic/meson_clk.h
diff -u src/sys/arch/arm/amlogic/meson_clk.h:1.1 src/sys/arch/arm/amlogic/meson_clk.h:1.2
--- src/sys/arch/arm/amlogic/meson_clk.h:1.1 Sat Jan 19 20:56:03 2019
+++ src/sys/arch/arm/amlogic/meson_clk.h Sun Jan 20 17:28:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: meson_clk.h,v 1.1 2019/01/19 20:56:03 jmcneill Exp $ */
+/* $NetBSD: meson_clk.h,v 1.2 2019/01/20 17:28:00 jmcneill Exp $ */
/*-
* Copyright (c) 2017-2019 Jared McNeill <[email protected]>
@@ -199,6 +199,7 @@ const char *meson_clk_mux_get_parent(str
[_id] = { \
.type = MESON_CLK_MUX, \
.base.name = (_name), \
+ .base.flags = CLK_SET_RATE_PARENT, \
.u.mux.parents = (_parents), \
.u.mux.nparents = __arraycount(_parents), \
.u.mux.reg = (_reg), \
@@ -236,6 +237,24 @@ u_int meson_clk_pll_get_rate(struct meso
const char *meson_clk_pll_get_parent(struct meson_clk_softc *,
struct meson_clk_clk *);
+#define MESON_CLK_PLL_RATE(_id, _name, _parent, _enable, _m, _n, _frac, _l, \
+ _reset, _setratefn, _flags) \
+ [_id] = { \
+ .type = MESON_CLK_PLL, \
+ .base.name = (_name), \
+ .u.pll.parent = (_parent), \
+ .u.pll.enable = _enable, \
+ .u.pll.m = _m, \
+ .u.pll.n = _n, \
+ .u.pll.frac = _frac, \
+ .u.pll.l = _l, \
+ .u.pll.reset = _reset, \
+ .u.pll.flags = (_flags), \
+ .set_rate = (_setratefn), \
+ .get_rate = meson_clk_pll_get_rate, \
+ .get_parent = meson_clk_pll_get_parent, \
+ }
+
#define MESON_CLK_PLL(_id, _name, _parent, _enable, _m, _n, _frac, _l, \
_reset, _flags) \
[_id] = { \
