Module Name: src
Committed By: skrll
Date: Fri Apr 12 21:12:21 UTC 2019
Modified Files:
src/sys/arch/mips/mips: spl.S
Log Message:
Typo in comment
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/mips/mips/spl.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/spl.S
diff -u src/sys/arch/mips/mips/spl.S:1.16 src/sys/arch/mips/mips/spl.S:1.17
--- src/sys/arch/mips/mips/spl.S:1.16 Fri Nov 18 16:23:40 2016
+++ src/sys/arch/mips/mips/spl.S Fri Apr 12 21:12:21 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: spl.S,v 1.16 2016/11/18 16:23:40 skrll Exp $ */
+/* $NetBSD: spl.S,v 1.17 2019/04/12 21:12:21 skrll Exp $ */
/*-
* Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
#include <mips/asm.h>
#include <mips/cpuregs.h>
-RCSID("$NetBSD: spl.S,v 1.16 2016/11/18 16:23:40 skrll Exp $")
+RCSID("$NetBSD: spl.S,v 1.17 2019/04/12 21:12:21 skrll Exp $")
#include "assym.h"
@@ -172,7 +172,7 @@ END(_splsw_splx)
STATIC_LEAF(_splsw_spl0)
INT_L v1, _C_LABEL(ipl_sr_map) + 4*IPL_NONE
PTR_L a3, L_CPU(MIPS_CURLWP)
- or v1, MIPS_SR_INT_IE # mask sure interrupts are on
+ or v1, MIPS_SR_INT_IE # make sure interrupts are on
xor v1, MIPS_INT_MASK # invert
mfc0 a0, MIPS_COP_0_STATUS
MFC0_HAZARD # load delay
