Module Name: src
Committed By: msaitoh
Date: Fri Dec 27 09:47:18 UTC 2019
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
s/defintion/definition/ in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.60 -r1.61 src/sys/arch/mips/mips/cache.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/cache.c
diff -u src/sys/arch/mips/mips/cache.c:1.60 src/sys/arch/mips/mips/cache.c:1.61
--- src/sys/arch/mips/mips/cache.c:1.60 Mon Sep 3 16:29:26 2018
+++ src/sys/arch/mips/mips/cache.c Fri Dec 27 09:47:18 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.c,v 1.60 2018/09/03 16:29:26 riastradh Exp $ */
+/* $NetBSD: cache.c,v 1.61 2019/12/27 09:47:18 msaitoh Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.60 2018/09/03 16:29:26 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.61 2019/12/27 09:47:18 msaitoh Exp $");
#include "opt_cputype.h"
#include "opt_mips_cache.h"
@@ -1406,7 +1406,7 @@ mips_config_cache_modern(uint32_t cpu_id
}
} else if (MIPS_PRID_CID(cpu_id) == MIPS_PRID_CID_MTI) {
/*
- * All MTI cores share a (mostly) common config7 defintion.
+ * All MTI cores share a (mostly) common config7 definition.
* Use it to determine if the caches have virtual aliases.
* If the core doesn't have a config7 register, its caches
* are too small or have too many ways to have aliases.
