CVS commit: src/sys/dev/mii

[SAITOH Masanobu]

Module Name:    src
Committed By:   msaitoh
Date:           Fri Mar 13 18:57:49 UTC 2020

Modified Files:
        src/sys/dev/mii: atphy.c

Log Message:
Fix a bug that atphy(4) doesn't work with Attansic L2 rev. 1.
Reported by Rocky Hotas.

- On ASUS M2N-MX SE Plus (NVIDIA MCP61 with Attansic L2 rev. 1), changing
  debug port 0x29's value makes the next PHY read fail with error.  Read any
  register to ignore this problem if the PHY is Attansic L2 revision 1.
  I don't know if this problem is from L2 rev. 1 itself or from the
  combination because I have only one machine which has L2 rev. "1".
  At least, ASUS eee pc 900 (Attansic L2 rev. "2") has no this problem.
- Add comment. AR8021 document has no description about the power saving
  control register(debug port 0x29).
- Add comment. AR8031 document says the lower 14 bits are reserved and the
  default value is 0x36d0. Shouldn't we clear those bits?
- I have no document neither L1(F1) nor L2(F2), so I don't know whether the
  debug port access is correct or not.

Tested with the following machines:
- ASUS P5B SE,         L1 rev. 5,            age(4)
- ASUS K50IJ,          L1 rev. 9,            ale(4)
- ASUS eee pc 900,     L2 rev. 2,            lii(4)
- ASUS M2N-MX SE Plus, L2 rev. 1,            nfe(4)
- Intel DP55WB,        82578(AR8021 rev. 2), wm(4)
- Dell inspiron 14z,   AR0835 rev. 9,        alc(4)


To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/dev/mii/atphy.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/dev/mii/atphy.c
diff -u src/sys/dev/mii/atphy.c:1.28 src/sys/dev/mii/atphy.c:1.29
--- src/sys/dev/mii/atphy.c:1.28	Fri Mar 13 04:44:34 2020
+++ src/sys/dev/mii/atphy.c	Fri Mar 13 18:57:49 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: atphy.c,v 1.28 2020/03/13 04:44:34 msaitoh Exp $ */
+/*	$NetBSD: atphy.c,v 1.29 2020/03/13 18:57:49 msaitoh Exp $ */
 /*	$OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $	*/
 
 /*-
@@ -33,7 +33,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.28 2020/03/13 04:44:34 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.29 2020/03/13 18:57:49 msaitoh Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -404,10 +404,30 @@ atphy_reset(struct mii_softc *sc)
 	uint16_t reg;
 	int i;
 
-	/* Take PHY out of power down mode. */
+	/*
+	 * Take PHY out of power down mode.
+	 *
+	 * XXX AR8021 document has no description about the power saving
+	 * control register. Shouldn't we write it?
+	 */
 	PHY_WRITE(sc, 29, 0x29);
+	/*
+	 * XXX AR8031 document says the lower 14 bits are reserved and the
+	 * default value is 0x36d0. Shouldn't we clear those bits?
+	 * I have no document neither L1(F1) nor L2(F2).
+	 */
 	PHY_WRITE(sc, 30, 0);
 
+	if ((sc->mii_mpd_model == MII_MODEL_ATTANSIC_L2)
+	    && (sc->mii_mpd_rev == 1)) {
+		/*
+		 * On NVIDIA MCP61 with Attansic L2 rev. 1, changing debug
+		 * port 0x29's value makes the next PHY read fail with error.
+		 * This is observed on ASUS M2N-MX SE Plus. Read any register
+		 * to ignore this problem.
+		 */
+		(void)PHY_READ(sc, ATPHY_SCR, &reg);
+	}
 	PHY_READ(sc, ATPHY_SCR, &reg);
 	/* Enable automatic crossover. */
 	reg |= ATPHY_SCR_AUTO_X_MODE;