Module Name: src Committed By: jmcneill Date: Mon May 25 19:48:38 UTC 2020
Modified Files: src/sys/dev/mii: brgphy.c brgphyreg.h Log Message: Add support for BCM54213PE RGMII clock delays, from OpenBSD To generate a diff of this commit: cvs rdiff -u -r1.89 -r1.90 src/sys/dev/mii/brgphy.c cvs rdiff -u -r1.11 -r1.12 src/sys/dev/mii/brgphyreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/dev/mii/brgphy.c diff -u src/sys/dev/mii/brgphy.c:1.89 src/sys/dev/mii/brgphy.c:1.90 --- src/sys/dev/mii/brgphy.c:1.89 Sat Mar 28 18:37:18 2020 +++ src/sys/dev/mii/brgphy.c Mon May 25 19:48:38 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: brgphy.c,v 1.89 2020/03/28 18:37:18 thorpej Exp $ */ +/* $NetBSD: brgphy.c,v 1.90 2020/05/25 19:48:38 jmcneill Exp $ */ /*- * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. @@ -62,7 +62,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.89 2020/03/28 18:37:18 thorpej Exp $"); +__KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.90 2020/05/25 19:48:38 jmcneill Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -118,7 +118,7 @@ static void brgphy_crc_bug(struct mii_so static void brgphy_disable_early_dac(struct mii_softc *); static void brgphy_jumbo_settings(struct mii_softc *); static void brgphy_eth_wirespeed(struct mii_softc *); - +static void brgphy_bcm54xx_clock_delay(struct mii_softc *); static const struct mii_phy_funcs brgphy_copper_funcs = { brgphy_service, brgphy_copper_status, brgphy_reset, @@ -460,6 +460,12 @@ setit: break; } break; + case MII_OUI_BROADCOM4: + switch (sc->mii_mpd_model) { + case MII_MODEL_BROADCOM4_BCM54213PE: + brgphy_bcm54xx_clock_delay(sc); + break; + } } } @@ -1242,3 +1248,30 @@ brgphy_eth_wirespeed(struct mii_softc *s PHY_READ(sc, BRGPHY_MII_AUXCTL, &val); PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); } + +static void +brgphy_bcm54xx_clock_delay(struct mii_softc *sc) +{ + uint16_t val; + + PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_SHADOW_MISC | + BRGPHY_AUXCTL_SHADOW_MISC << BRGPHY_AUXCTL_MISC_READ_SHIFT); + PHY_READ(sc, BRGPHY_MII_AUXCTL, &val); + val &= BRGPHY_AUXCTL_MISC_DATA_MASK; + if (sc->mii_flags & MIIF_RXID) + val |= BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN; + else + val &= ~BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN; + PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_MISC_WRITE_EN | + BRGPHY_AUXCTL_SHADOW_MISC | val); + + PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_CLK_CTRL); + PHY_READ(sc, BRGPHY_MII_SHADOW_1C, &val); + val &= BRGPHY_SHADOW_1C_DATA_MASK; + if (sc->mii_flags & MIIF_TXID) + val |= BRGPHY_SHADOW_1C_GTXCLK_EN; + else + val &= ~BRGPHY_SHADOW_1C_GTXCLK_EN; + PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_WRITE_EN | + BRGPHY_SHADOW_1C_CLK_CTRL | val); +} Index: src/sys/dev/mii/brgphyreg.h diff -u src/sys/dev/mii/brgphyreg.h:1.11 src/sys/dev/mii/brgphyreg.h:1.12 --- src/sys/dev/mii/brgphyreg.h:1.11 Thu Apr 11 09:14:07 2019 +++ src/sys/dev/mii/brgphyreg.h Mon May 25 19:48:38 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: brgphyreg.h,v 1.11 2019/04/11 09:14:07 msaitoh Exp $ */ +/* $NetBSD: brgphyreg.h,v 1.12 2020/05/25 19:48:38 jmcneill Exp $ */ /* * Copyright (c) 2000 @@ -192,6 +192,17 @@ /* Begin: PHY register values for the 5706 PHY */ /*******************************************************/ +/* + * Aux control shadow register, bits 0-2 select function (0x00 to + * 0x07). + */ +#define BRGPHY_AUXCTL_SHADOW_MISC 0x07 +#define BRGPHY_AUXCTL_MISC_DATA_MASK 0x7ff8 +#define BRGPHY_AUXCTL_MISC_READ_SHIFT 12 +#define BRGPHY_AUXCTL_MISC_WRITE_EN 0x8000 +#define BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN 0x0200 +#define BRGPHY_AUXCTL_MISC_WIRESPEED_EN 0x0010 + /* * Shadow register 0x1C, bit 15 is write enable, * bits 14-10 select function (0x00 to 0x1F). @@ -199,6 +210,11 @@ #define BRGPHY_MII_SHADOW_1C 0x1C #define BRGPHY_SHADOW_1C_WRITE_EN 0x8000 #define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00 +#define BRGPHY_SHADOW_1C_DATA_MASK 0x03FF + +/* Shadow 0x1C Clock Alignment Control Register (select value 0x03) */ +#define BRGPHY_SHADOW_1C_CLK_CTRL (0x03 << 10) +#define BRGPHY_SHADOW_1C_GTXCLK_EN 0x0200 /* Shadow 0x1C Mode Control Register (select value 0x1F) */ #define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10)