Module Name: src
Committed By: jmcneill
Date: Fri Dec 11 21:40:50 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c gicv3_its.c
Log Message:
Preserve ST Lower and Upper fields when clearing Mask bit in the MSI-X
vector control register.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gic_v2m.c
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_v2m.c
diff -u src/sys/arch/arm/cortex/gic_v2m.c:1.9 src/sys/arch/arm/cortex/gic_v2m.c:1.10
--- src/sys/arch/arm/cortex/gic_v2m.c:1.9 Thu May 7 16:20:40 2020
+++ src/sys/arch/arm/cortex/gic_v2m.c Fri Dec 11 21:40:50 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.c,v 1.9 2020/05/07 16:20:40 jmcneill Exp $ */
+/* $NetBSD: gic_v2m.c,v 1.10 2020/12/11 21:40:50 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.9 2020/05/07 16:20:40 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.10 2020/12/11 21:40:50 jmcneill Exp $");
#include <sys/param.h>
#include <sys/kmem.h>
@@ -183,6 +183,7 @@ gic_v2m_msix_enable(struct gic_v2m_frame
pci_chipset_tag_t pc = pa->pa_pc;
pcitag_t tag = pa->pa_tag;
pcireg_t ctl;
+ uint32_t val;
int off;
if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL))
@@ -198,7 +199,9 @@ gic_v2m_msix_enable(struct gic_v2m_frame
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32));
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, data);
- bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0);
+ val = bus_space_read_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL);
+ val &= ~PCI_MSIX_VECTCTL_MASK;
+ bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, val);
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
ctl |= PCI_MSIX_CTL_ENABLE;
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.28 src/sys/arch/arm/cortex/gicv3_its.c:1.29
--- src/sys/arch/arm/cortex/gicv3_its.c:1.28 Thu Sep 24 08:50:09 2020
+++ src/sys/arch/arm/cortex/gicv3_its.c Fri Dec 11 21:40:50 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.28 2020/09/24 08:50:09 ryo Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.29 2020/12/11 21:40:50 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.28 2020/09/24 08:50:09 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.29 2020/12/11 21:40:50 jmcneill Exp $");
#include <sys/param.h>
#include <sys/kmem.h>
@@ -429,6 +429,7 @@ gicv3_its_msix_enable(struct gicv3_its *
pci_chipset_tag_t pc = pa->pa_pc;
pcitag_t tag = pa->pa_tag;
pcireg_t ctl;
+ uint32_t val;
int off;
if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL))
@@ -439,7 +440,9 @@ gicv3_its_msix_enable(struct gicv3_its *
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr);
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32));
bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, lpi - its->its_pic->pic_irqbase);
- bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0);
+ val = bus_space_read_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL);
+ val &= ~PCI_MSIX_VECTCTL_MASK;
+ bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, val);
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
ctl |= PCI_MSIX_CTL_ENABLE;
