Module Name: src
Committed By: jmcneill
Date: Sun Feb 21 15:45:30 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Apply PMR optimizations from gicv3
To generate a diff of this commit:
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.44 src/sys/arch/arm/cortex/gic.c:1.45
--- src/sys/arch/arm/cortex/gic.c:1.44 Tue Feb 9 14:24:14 2021
+++ src/sys/arch/arm/cortex/gic.c Sun Feb 21 15:45:30 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.44 2021/02/09 14:24:14 jakllsch Exp $ */
+/* $NetBSD: gic.c,v 1.45 2021/02/21 15:45:30 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.44 2021/02/09 14:24:14 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.45 2021/02/21 15:45:30 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -222,9 +222,14 @@ static void
armgic_set_priority(struct pic_softc *pic, int ipl)
{
struct armgic_softc * const sc = PICTOSOFTC(pic);
+ struct cpu_info * const ci = curcpu();
const uint32_t priority = armgic_ipl_to_priority(ipl);
- gicc_write(sc, GICC_PMR, priority);
+ if (priority > ci->ci_hwpl) {
+ /* Lowering priority mask */
+ ci->ci_hwpl = priority;
+ gicc_write(sc, GICC_PMR, priority);
+ }
}
#ifdef MULTIPROCESSOR
@@ -322,6 +327,12 @@ armgic_irq_handler(void *tf)
ci->ci_data.cpu_nintr++;
+ const uint32_t priority = armgic_ipl_to_priority(old_ipl);
+ if (ci->ci_hwpl != priority) {
+ ci->ci_hwpl = priority;
+ gicc_write(sc, GICC_PMR, priority);
+ }
+
for (;;) {
uint32_t iar = gicc_read(sc, GICC_IAR);
uint32_t irq = __SHIFTOUT(iar, GICC_IAR_IRQ);
@@ -365,7 +376,7 @@ armgic_irq_handler(void *tf)
ipl, ci->ci_cpl,
gicc_read(sc, GICC_PMR));
gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl));
- ci->ci_cpl = ipl;
+ ci->ci_hwpl = ci->ci_cpl = ipl;
}
ENABLE_INTERRUPT();
pic_dispatch(is, tf);
@@ -527,6 +538,7 @@ armgic_cpu_init(struct pic_softc *pic, s
sc->sc_enabled_local);
}
}
+ ci->ci_hwpl = armgic_ipl_to_priority(ci->ci_cpl);
gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl)); // set PMR
gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt
ENABLE_INTERRUPT(); // allow IRQ exceptions
