Module Name: src
Committed By: jmcneill
Date: Mon Mar 1 11:29:14 UTC 2021
Modified Files:
src/sys/arch/aarch64/include: locore.h
src/sys/arch/arm/include: cpufunc.h
src/sys/arch/arm/pic: pic_splfuncs.c
Log Message:
Add DISABLE_INTERRUPT_SAVE(), like DISABLE_INTERRUPT() but also returns
the previous state.
Use DISABLE_INTERRUPT_SAVE()/ENABLE_INTERRUPT() in pic_splfuncs instead
of cpsid()/cpsie(). The difference here is the caller no longer specifies
which bits to disable and enable; on arm32 we continue to use I32_bit and
on aarch64 we now consistently toggle both IRQ and FIQ state.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/include/locore.h
cvs rdiff -u -r1.87 -r1.88 src/sys/arch/arm/include/cpufunc.h
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/pic/pic_splfuncs.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/include/locore.h
diff -u src/sys/arch/aarch64/include/locore.h:1.8 src/sys/arch/aarch64/include/locore.h:1.9
--- src/sys/arch/aarch64/include/locore.h:1.8 Sat Feb 20 19:27:35 2021
+++ src/sys/arch/aarch64/include/locore.h Mon Mar 1 11:29:14 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.8 2021/02/20 19:27:35 jmcneill Exp $ */
+/* $NetBSD: locore.h,v 1.9 2021/03/01 11:29:14 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -58,11 +58,12 @@
#define cpsie(psw) daif_enable((psw))
#define cpsid(psw) daif_disable((psw))
-
-#define ENABLE_INTERRUPT() \
+#define ENABLE_INTERRUPT() \
reg_daifclr_write((DAIF_I|DAIF_F) >> DAIF_SETCLR_SHIFT)
-#define DISABLE_INTERRUPT() \
+#define DISABLE_INTERRUPT() \
reg_daifset_write((DAIF_I|DAIF_F) >> DAIF_SETCLR_SHIFT)
+#define DISABLE_INTERRUPT_SAVE() \
+ daif_disable(DAIF_I|DAIF_F)
#define DAIF_MASK (DAIF_D|DAIF_A|DAIF_I|DAIF_F)
Index: src/sys/arch/arm/include/cpufunc.h
diff -u src/sys/arch/arm/include/cpufunc.h:1.87 src/sys/arch/arm/include/cpufunc.h:1.88
--- src/sys/arch/arm/include/cpufunc.h:1.87 Sun Feb 7 21:15:40 2021
+++ src/sys/arch/arm/include/cpufunc.h Mon Mar 1 11:29:14 2021
@@ -353,8 +353,9 @@ enable_interrupts(uint32_t mask)
#define restore_interrupts(old_cpsr) \
(__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
-#define ENABLE_INTERRUPT() cpsie(I32_bit)
-#define DISABLE_INTERRUPT() cpsid(I32_bit)
+#define ENABLE_INTERRUPT() cpsie(I32_bit)
+#define DISABLE_INTERRUPT() cpsid(I32_bit)
+#define DISABLE_INTERRUPT_SAVE() cpsid(I32_bit)
static inline void cpsie(register_t psw) __attribute__((__unused__));
static inline register_t cpsid(register_t psw) __attribute__((__unused__));
Index: src/sys/arch/arm/pic/pic_splfuncs.c
diff -u src/sys/arch/arm/pic/pic_splfuncs.c:1.18 src/sys/arch/arm/pic/pic_splfuncs.c:1.19
--- src/sys/arch/arm/pic/pic_splfuncs.c:1.18 Mon Feb 22 21:16:25 2021
+++ src/sys/arch/arm/pic/pic_splfuncs.c Mon Mar 1 11:29:14 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pic_splfuncs.c,v 1.18 2021/02/22 21:16:25 jmcneill Exp $ */
+/* $NetBSD: pic_splfuncs.c,v 1.19 2021/03/01 11:29:14 jmcneill Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -28,7 +28,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pic_splfuncs.c,v 1.18 2021/02/22 21:16:25 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pic_splfuncs.c,v 1.19 2021/03/01 11:29:14 jmcneill Exp $");
#define _INTR_PRIVATE
#include <sys/param.h>
@@ -75,12 +75,13 @@ _spllower(int newipl)
const int oldipl = ci->ci_cpl;
KDASSERT(panicstr || newipl <= ci->ci_cpl);
if (newipl < ci->ci_cpl) {
- register_t psw = cpsid(I32_bit);
+ register_t psw = DISABLE_INTERRUPT_SAVE();
ci->ci_intr_depth++;
pic_do_pending_ints(psw, newipl, NULL);
ci->ci_intr_depth--;
- if ((psw & I32_bit) == 0 || newipl == IPL_NONE)
- cpsie(I32_bit);
+ if ((psw & I32_bit) == 0 || newipl == IPL_NONE) {
+ ENABLE_INTERRUPT();
+ }
cpu_dosoftints();
}
return oldipl;
@@ -113,7 +114,7 @@ splx(int savedipl)
static void __noinline
splx_dopendingints(struct cpu_info *ci, const int savedipl)
{
- const register_t psw = cpsid(I32_bit);
+ const register_t psw = DISABLE_INTERRUPT_SAVE();
ci->ci_intr_depth++;
while ((ci->ci_pending_ipls & ~__BIT(savedipl)) > __BIT(savedipl)) {
KASSERT(ci->ci_pending_ipls < __BIT(NIPL));
@@ -131,7 +132,7 @@ splx_dopendingints(struct cpu_info *ci,
}
ci->ci_intr_depth--;
if ((psw & I32_bit) == 0) {
- cpsie(I32_bit);
+ ENABLE_INTERRUPT();
}
}
#endif
