Module Name: src
Committed By: matt
Date: Sun Feb 20 07:55:21 UTC 2011
Modified Files:
src/sys/arch/ews4800mips/conf: files.ews4800mips
src/sys/arch/ews4800mips/ews4800mips: autoconf.c bus_dma.c cpu.c
interrupt.c machdep.c mainbus.c tr2.c tr2_intr.c tr2a.c tr2a_intr.c
src/sys/arch/ews4800mips/include: intr.h sbdvar.h
Log Message:
Merge forward matt-nb5-mips64
Adapt to new interrupt/spl framework
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/ews4800mips/conf/files.ews4800mips
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/ews4800mips/ews4800mips/autoconf.c \
src/sys/arch/ews4800mips/ews4800mips/interrupt.c
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/ews4800mips/ews4800mips/bus_dma.c \
src/sys/arch/ews4800mips/ews4800mips/tr2_intr.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/ews4800mips/ews4800mips/cpu.c
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/ews4800mips/ews4800mips/machdep.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/ews4800mips/ews4800mips/mainbus.c \
src/sys/arch/ews4800mips/ews4800mips/tr2.c \
src/sys/arch/ews4800mips/ews4800mips/tr2a.c
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/ews4800mips/include/intr.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/ews4800mips/include/sbdvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/ews4800mips/conf/files.ews4800mips
diff -u src/sys/arch/ews4800mips/conf/files.ews4800mips:1.4 src/sys/arch/ews4800mips/conf/files.ews4800mips:1.5
--- src/sys/arch/ews4800mips/conf/files.ews4800mips:1.4 Fri Aug 21 03:53:18 2009
+++ src/sys/arch/ews4800mips/conf/files.ews4800mips Sun Feb 20 07:55:20 2011
@@ -1,4 +1,4 @@
-# $NetBSD: files.ews4800mips,v 1.4 2009/08/21 03:53:18 thorpej Exp $
+# $NetBSD: files.ews4800mips,v 1.5 2011/02/20 07:55:20 matt Exp $
maxpartitions 16
@@ -6,7 +6,6 @@
include "arch/ews4800mips/conf/majors.ews4800mips"
-file arch/mips/mips/softintr.c
file arch/mips/mips/mips3_clock.c
file arch/ews4800mips/ews4800mips/autoconf.c
Index: src/sys/arch/ews4800mips/ews4800mips/autoconf.c
diff -u src/sys/arch/ews4800mips/ews4800mips/autoconf.c:1.7 src/sys/arch/ews4800mips/ews4800mips/autoconf.c:1.8
--- src/sys/arch/ews4800mips/ews4800mips/autoconf.c:1.7 Mon Apr 28 20:23:18 2008
+++ src/sys/arch/ews4800mips/ews4800mips/autoconf.c Sun Feb 20 07:55:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.7 2008/04/28 20:23:18 martin Exp $ */
+/* $NetBSD: autoconf.c,v 1.8 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2001, 2004 The NetBSD Foundation, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.7 2008/04/28 20:23:18 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.8 2011/02/20 07:55:20 matt Exp $");
#include "opt_sbd.h"
@@ -35,6 +35,7 @@
#include <sys/systm.h>
#include <sys/conf.h>
#include <sys/device.h>
+#include <sys/intr.h>
#include <machine/sbdvar.h>
#include <machine/disklabel.h>
@@ -50,7 +51,7 @@
splhigh();
if (config_rootfound("mainbus", NULL) == NULL)
panic("no mainbus found");
- _splnone();
+ spl0();
}
void
Index: src/sys/arch/ews4800mips/ews4800mips/interrupt.c
diff -u src/sys/arch/ews4800mips/ews4800mips/interrupt.c:1.7 src/sys/arch/ews4800mips/ews4800mips/interrupt.c:1.8
--- src/sys/arch/ews4800mips/ews4800mips/interrupt.c:1.7 Mon Dec 20 00:25:33 2010
+++ src/sys/arch/ews4800mips/ews4800mips/interrupt.c Sun Feb 20 07:55:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.7 2010/12/20 00:25:33 matt Exp $ */
+/* $NetBSD: interrupt.c,v 1.8 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2004 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.7 2010/12/20 00:25:33 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.8 2011/02/20 07:55:20 matt Exp $");
#include <sys/param.h>
#include <sys/intr.h>
@@ -38,8 +38,7 @@
#include <machine/sbdvar.h>
-const uint32_t *ipl_sr_bits;
-static void (*platform_intr)(uint32_t, uint32_t, vaddr_t, uint32_t);
+static void (*platform_intr)(int, vaddr_t, uint32_t);
void
intr_init(void)
@@ -64,22 +63,9 @@
}
void
-cpu_intr(uint32_t status, uint32_t cause, vaddr_t pc, uint32_t ipending)
+cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
- struct cpu_info *ci;
+ curcpu()->ci_data.cpu_nintr++;
- ci = curcpu();
- ci->ci_data.cpu_nintr++;
-
- ci->ci_idepth++;
- (*platform_intr)(status, cause, pc, ipending);
- ci->ci_idepth--;
-
-#ifdef __HAVE_FAST_SOFTINTS
- ipending &= (MIPS_SOFT_INT_MASK_1 | MIPS_SOFT_INT_MASK_0);
- if (ipending == 0)
- return;
- _clrsoftintr(ipending);
- softintr_dispatch(ipending);
-#endif
+ (*platform_intr)(ppl, pc, status);
}
Index: src/sys/arch/ews4800mips/ews4800mips/bus_dma.c
diff -u src/sys/arch/ews4800mips/ews4800mips/bus_dma.c:1.10 src/sys/arch/ews4800mips/ews4800mips/bus_dma.c:1.11
--- src/sys/arch/ews4800mips/ews4800mips/bus_dma.c:1.10 Fri Aug 21 03:53:18 2009
+++ src/sys/arch/ews4800mips/ews4800mips/bus_dma.c Sun Feb 20 07:55:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_dma.c,v 1.10 2009/08/21 03:53:18 thorpej Exp $ */
+/* $NetBSD: bus_dma.c,v 1.11 2011/02/20 07:55:20 matt Exp $ */
/*
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.10 2009/08/21 03:53:18 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.11 2011/02/20 07:55:20 matt Exp $");
/* #define BUS_DMA_DEBUG */
#include <sys/param.h>
@@ -502,22 +502,24 @@
mips_dcache_wbinv_range(start, minlen);
break;
- case BUS_DMASYNC_PREREAD:
+ case BUS_DMASYNC_PREREAD: {
+ const struct mips_cache_info * const mci = &mips_cache_info;
end = start + minlen;
- preboundary = start & ~mips_dcache_align_mask;
- firstboundary = (start + mips_dcache_align_mask)
- & ~mips_dcache_align_mask;
- lastboundary = end & ~mips_dcache_align_mask;
+ preboundary = start & ~mci->mci_dcache_align_mask;
+ firstboundary = (start + mci->mci_dcache_align_mask)
+ & ~mci->mci_dcache_align_mask;
+ lastboundary = end & ~mci->mci_dcache_align_mask;
if (preboundary < start && preboundary < lastboundary)
mips_dcache_wbinv_range(preboundary,
- mips_dcache_align);
+ mci->mci_dcache_align);
if (firstboundary < lastboundary)
mips_dcache_inv_range(firstboundary,
lastboundary - firstboundary);
if (lastboundary < end)
mips_dcache_wbinv_range(lastboundary,
- mips_dcache_align);
+ mci->mci_dcache_align);
break;
+ }
case BUS_DMASYNC_PREWRITE:
mips_dcache_wb_range(start, minlen);
@@ -540,12 +542,11 @@
bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs,
int flags)
{
- extern paddr_t avail_start, avail_end;
+ extern paddr_t mips_avail_start, mips_avail_end;
return (_bus_dmamem_alloc_range_common(t, size, alignment, boundary,
- segs, nsegs, rsegs, flags,
- avail_start /*low*/,
- avail_end - PAGE_SIZE /*high*/));
+ segs, nsegs, rsegs, flags,
+ mips_avail_start /*low*/, mips_avail_end - PAGE_SIZE /*high*/));
}
/*
Index: src/sys/arch/ews4800mips/ews4800mips/tr2_intr.c
diff -u src/sys/arch/ews4800mips/ews4800mips/tr2_intr.c:1.10 src/sys/arch/ews4800mips/ews4800mips/tr2_intr.c:1.11
--- src/sys/arch/ews4800mips/ews4800mips/tr2_intr.c:1.10 Mon Apr 28 20:23:18 2008
+++ src/sys/arch/ews4800mips/ews4800mips/tr2_intr.c Sun Feb 20 07:55:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: tr2_intr.c,v 1.10 2008/04/28 20:23:18 martin Exp $ */
+/* $NetBSD: tr2_intr.c,v 1.11 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@@ -30,12 +30,15 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tr2_intr.c,v 1.10 2008/04/28 20:23:18 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tr2_intr.c,v 1.11 2011/02/20 07:55:20 matt Exp $");
+#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
-#include <sys/device.h>
+#include <sys/evcnt.h>
+#include <sys/cpu.h>
+#include <sys/lwp.h>
#include <sys/intr.h>
#include <machine/locore.h> /* mips3_cp0* */
@@ -47,23 +50,24 @@
SBD_DECL(tr2);
-const uint32_t tr2_sr_bits[_IPL_N] = {
- [IPL_NONE] = 0,
- [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
- [IPL_SOFTNET] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
- [IPL_VM] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_4,
- [IPL_SCHED] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_4 |
- MIPS_INT_MASK_5,
+const struct ipl_sr_map tr2_ipl_sr_map = {
+ {
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_SOFT_INT_MASK
+ | MIPS_INT_MASK_0
+ | MIPS_INT_MASK_2
+ | MIPS_INT_MASK_4,
+ [IPL_SCHED] = MIPS_SOFT_INT_MASK
+ | MIPS_INT_MASK_0
+ | MIPS_INT_MASK_2
+ | MIPS_INT_MASK_4
+ | MIPS_INT_MASK_5,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
/* !!! TEST !!! VME INTERRUPT IS NOT MASKED */
+ },
};
#define NIRQ 8
@@ -139,121 +143,116 @@
}
void
-tr2_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+tr2_intr(int ppl, vaddr_t pc, uint32_t status)
{
struct tr2_intr_handler *ih;
struct clockframe cf;
- uint32_t r, handled;
+ uint32_t r, ipending;
+ int ipl;
- handled = 0;
+ while (ppl < (ipl = splintr(&ipending))) {
+ if (ipending & MIPS_INT_MASK_5) { /* CLOCK */
+ cf.pc = pc;
+ cf.sr = status;
+ cf.intr = (curcpu()->ci_idepth > 0);
- if (ipending & MIPS_INT_MASK_5) { /* CLOCK */
- cf.pc = pc;
- cf.sr = status;
+ *PICNIC_INT5_STATUS_REG = 0;
+ r = *PICNIC_INT5_STATUS_REG;
- *PICNIC_INT5_STATUS_REG = 0;
- r = *PICNIC_INT5_STATUS_REG;
-
- hardclock(&cf);
- timer_tr2_ev.ev_count++;
- handled |= MIPS_INT_MASK_5;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
+ hardclock(&cf);
+ timer_tr2_ev.ev_count++;
+ }
- if (ipending & MIPS_INT_MASK_4) { /* KBD, MOUSE, SERIAL */
- r = *PICNIC_INT4_STATUS_REG;
+ if (ipending & MIPS_INT_MASK_4) { /* KBD, MOUSE, SERIAL */
+ r = *PICNIC_INT4_STATUS_REG;
- if (r & PICNIC_INT_KBMS) {
- ih = &tr2_intr_handler[0];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
+ if (r & PICNIC_INT_KBMS) {
+ ih = &tr2_intr_handler[0];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ r &= ~PICNIC_INT_KBMS;
}
- r &= ~PICNIC_INT_KBMS;
- }
- if (r & PICNIC_INT_SERIAL) {
+ if (r & PICNIC_INT_SERIAL) {
#if 0
- printf("SIO interrupt\n");
+ printf("SIO interrupt\n");
#endif
- ih = &tr2_intr_handler[2];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
+ ih = &tr2_intr_handler[2];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ r &= ~PICNIC_INT_SERIAL;
}
- r &= ~PICNIC_INT_SERIAL;
}
- handled |= MIPS_INT_MASK_4;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
+ if (ipending & MIPS_INT_MASK_3) { /* VME */
+ printf("VME interrupt\n");
- if (ipending & MIPS_INT_MASK_3) { /* VME */
- printf("VME interrupt\n");
-
- r = *(volatile uint32_t *)0xbfb00018; /* NABI? */
- if ((r & 0x10) != 0) {
- /* vme high interrupt */
- } else if ((r & 0x4) != 0) {
- /* vme lo interrupt */
- } else {
- /* error */
+ r = *(volatile uint32_t *)0xbfb00018; /* NABI? */
+ if ((r & 0x10) != 0) {
+ /* vme high interrupt */
+ } else if ((r & 0x4) != 0) {
+ /* vme lo interrupt */
+ } else {
+ /* error */
+ }
}
- }
- if (ipending & MIPS_INT_MASK_2) { /* ETHER, SCSI */
- r = *PICNIC_INT2_STATUS_REG;
+ if (ipending & MIPS_INT_MASK_2) { /* ETHER, SCSI */
+ r = *PICNIC_INT2_STATUS_REG;
- if (r & PICNIC_INT_ETHER) {
- ih = &tr2_intr_handler[6];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
+ if (r & PICNIC_INT_ETHER) {
+ ih = &tr2_intr_handler[6];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ r &= ~PICNIC_INT_ETHER;
}
- r &= ~PICNIC_INT_ETHER;
- }
- if (r & PICNIC_INT_SCSI) {
- ih = &tr2_intr_handler[5];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
+ if (r & PICNIC_INT_SCSI) {
+ ih = &tr2_intr_handler[5];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ r &= ~PICNIC_INT_SCSI;
}
- r &= ~PICNIC_INT_SCSI;
- }
- if ((r & PICNIC_INT_FDDLPT) &&
- ((cause & status) & MIPS_INT_MASK_5)) {
+ if ((r & PICNIC_INT_FDDLPT) &&
+ (ipending & MIPS_INT_MASK_5)) {
#ifdef DEBUG
- printf("FDD LPT interrupt\n");
+ printf("FDD LPT interrupt\n");
#endif
- ih = &tr2_intr_handler[7];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
+ ih = &tr2_intr_handler[7];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ r &= ~PICNIC_INT_FDDLPT;
}
- r &= ~PICNIC_INT_FDDLPT;
}
- handled |= MIPS_INT_MASK_2;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
-
- if (ipending & MIPS_INT_MASK_1)
- panic("unknown interrupt INT1\n");
+ if (ipending & MIPS_INT_MASK_1)
+ panic("unknown interrupt INT1\n");
- if (ipending & MIPS_INT_MASK_0) { /* FDD, PRINTER */
- printf("printer, printer interrupt\n");
- r = *PICNIC_INT0_STATUS_REG;
- if (r & PICNIC_INT_FDDLPT) {
- printf("FDD, Printer interrupt.\n");
- } else {
- printf("unknown interrupt INT0\n");
+ if (ipending & MIPS_INT_MASK_0) { /* FDD, PRINTER */
+#ifdef DEBUG
+ printf("printer, printer interrupt\n");
+#endif
+ r = *PICNIC_INT0_STATUS_REG;
+ if (r & PICNIC_INT_FDDLPT) {
+#ifdef DEBUG
+ printf("FDD, Printer interrupt.\n");
+#endif
+ } else {
+ printf("unknown interrupt INT0\n");
+ }
}
- handled |= MIPS_INT_MASK_0;
}
- cause &= ~handled;
- _splset(((status & ~cause) & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
}
void
Index: src/sys/arch/ews4800mips/ews4800mips/cpu.c
diff -u src/sys/arch/ews4800mips/ews4800mips/cpu.c:1.3 src/sys/arch/ews4800mips/ews4800mips/cpu.c:1.4
--- src/sys/arch/ews4800mips/ews4800mips/cpu.c:1.3 Fri Apr 4 16:33:05 2008
+++ src/sys/arch/ews4800mips/ews4800mips/cpu.c Sun Feb 20 07:55:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.3 2008/04/04 16:33:05 tsutsui Exp $ */
+/* $NetBSD: cpu.c,v 1.4 2011/02/20 07:55:20 matt Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
@@ -26,18 +26,19 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3 2008/04/04 16:33:05 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.4 2011/02/20 07:55:20 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
+#include <sys/cpu.h>
#include <machine/autoconf.h>
#include "ioconf.h"
-int cpumatch(device_t, cfdata_t, void *);
-void cpuattach(device_t, device_t, void *);
+static int cpumatch(device_t, cfdata_t, void *);
+static void cpuattach(device_t, device_t, void *);
CFATTACH_DECL_NEW(cpu, 0,
cpumatch, cpuattach, NULL, NULL);
@@ -60,8 +61,13 @@
cpuattach(device_t parent, device_t self, void *aux)
{
+ struct cpu_info * const ci = curcpu();
+
+ ci->ci_dev = self;
+ self->dv_private = ci;
+
aprint_normal(": ");
cpu_attached = 1;
- cpu_identify();
+ cpu_identify(self);
}
Index: src/sys/arch/ews4800mips/ews4800mips/machdep.c
diff -u src/sys/arch/ews4800mips/ews4800mips/machdep.c:1.23 src/sys/arch/ews4800mips/ews4800mips/machdep.c:1.24
--- src/sys/arch/ews4800mips/ews4800mips/machdep.c:1.23 Tue May 4 15:32:31 2010
+++ src/sys/arch/ews4800mips/ews4800mips/machdep.c Sun Feb 20 07:55:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.23 2010/05/04 15:32:31 tsutsui Exp $ */
+/* $NetBSD: machdep.c,v 1.24 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2001, 2004, 2005 The NetBSD Foundation, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.23 2010/05/04 15:32:31 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.24 2011/02/20 07:55:20 matt Exp $");
#include "opt_ddb.h"
@@ -88,7 +88,7 @@
mach_init(int argc, char *argv[], struct bootinfo *bi)
{
extern char kernel_text[], edata[], end[];
- vaddr_t v;
+ void *v;
int i;
/* Clear BSS */
@@ -115,7 +115,7 @@
sbd_init();
__asm volatile("move %0, $29" : "=r"(v));
- printf("kernel_text=%p edata=%p end=%p sp=%" PRIxVADDR "\n",
+ printf("kernel_text=%p edata=%p end=%p sp=%p\n",
kernel_text, edata, end, v);
option(argc, argv, bi);
@@ -133,7 +133,7 @@
*/
cn_tab = NULL;
- mips_vector_init();
+ mips_vector_init(NULL, false);
memcpy((void *)0x80000200, ews4800mips_nmi_vec, 32); /* NMI */
mips_dcache_wbinv_all();
@@ -143,7 +143,7 @@
curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz;
curcpu()->ci_divisor_delay =
((curcpu()->ci_cpu_freq + 500000) / 1000000);
- if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) {
+ if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) {
curcpu()->ci_cycles_per_hz /= 2;
curcpu()->ci_divisor_delay /= 2;
}
@@ -254,8 +254,7 @@
static int waittime = -1;
/* Take a snapshot before clobbering any registers. */
- if (curlwp)
- savectx(curpcb);
+ savectx(curpcb);
if (cold) {
howto |= RB_HALT;
Index: src/sys/arch/ews4800mips/ews4800mips/mainbus.c
diff -u src/sys/arch/ews4800mips/ews4800mips/mainbus.c:1.4 src/sys/arch/ews4800mips/ews4800mips/mainbus.c:1.5
--- src/sys/arch/ews4800mips/ews4800mips/mainbus.c:1.4 Mon Apr 28 20:23:18 2008
+++ src/sys/arch/ews4800mips/ews4800mips/mainbus.c Sun Feb 20 07:55:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: mainbus.c,v 1.4 2008/04/28 20:23:18 martin Exp $ */
+/* $NetBSD: mainbus.c,v 1.5 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2001, 2004, 2005 The NetBSD Foundation, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.4 2008/04/28 20:23:18 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.5 2011/02/20 07:55:20 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -59,7 +59,7 @@
mainbus_attach(device_t parent, device_t self, void *aux)
{
struct mainbus_attach_args ma;
- const char **p;
+ const char * const *p;
mainbus_found = 1;
aprint_normal("\n");
Index: src/sys/arch/ews4800mips/ews4800mips/tr2.c
diff -u src/sys/arch/ews4800mips/ews4800mips/tr2.c:1.4 src/sys/arch/ews4800mips/ews4800mips/tr2.c:1.5
--- src/sys/arch/ews4800mips/ews4800mips/tr2.c:1.4 Mon Nov 15 06:23:05 2010
+++ src/sys/arch/ews4800mips/ews4800mips/tr2.c Sun Feb 20 07:55:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: tr2.c,v 1.4 2010/11/15 06:23:05 uebayasi Exp $ */
+/* $NetBSD: tr2.c,v 1.5 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@@ -30,8 +30,9 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tr2.c,v 1.4 2010/11/15 06:23:05 uebayasi Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tr2.c,v 1.5 2011/02/20 07:55:20 matt Exp $");
+#define __INTR_PRIVATE
#include "fb_sbdio.h"
#include "kbms_sbdio.h"
#include "zsc_sbdio.h"
@@ -60,7 +61,7 @@
SBD_DECL(tr2);
/* EWS4800/350 mainbus device list */
-static const char *tr2_mainbusdevs[] =
+static const char * const tr2_mainbusdevs[] =
{
"sbdio",
#ifdef notyet
@@ -103,7 +104,7 @@
platform.mainbusdevs = tr2_mainbusdevs;
platform.sbdiodevs = tr2_sbdiodevs;
- ipl_sr_bits = tr2_sr_bits;
+ ipl_sr_map = tr2_ipl_sr_map;
kseg2iobufsize = 0x02000000; /* 32MB for VME and framebuffer */
@@ -122,7 +123,7 @@
tr2_cache_config(void)
{
- mips_sdcache_size = 1024 * 1024; /* 1MB L2-cache */
+ mips_cache_info.mci_sdcache_size = 1024 * 1024; /* 1MB L2-cache */
}
void
Index: src/sys/arch/ews4800mips/ews4800mips/tr2a.c
diff -u src/sys/arch/ews4800mips/ews4800mips/tr2a.c:1.4 src/sys/arch/ews4800mips/ews4800mips/tr2a.c:1.5
--- src/sys/arch/ews4800mips/ews4800mips/tr2a.c:1.4 Mon Nov 15 06:23:05 2010
+++ src/sys/arch/ews4800mips/ews4800mips/tr2a.c Sun Feb 20 07:55:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: tr2a.c,v 1.4 2010/11/15 06:23:05 uebayasi Exp $ */
+/* $NetBSD: tr2a.c,v 1.5 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@@ -30,8 +30,9 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tr2a.c,v 1.4 2010/11/15 06:23:05 uebayasi Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tr2a.c,v 1.5 2011/02/20 07:55:20 matt Exp $");
+#define __INTR_PRIVATE
#include "fb_sbdio.h"
#include "kbms_sbdio.h"
#include "zsc_sbdio.h"
@@ -60,7 +61,7 @@
SBD_DECL(tr2a);
/* EWS4800/360 bus list */
-static const char *tr2a_mainbusdevs[] = {
+static const char * const tr2a_mainbusdevs[] = {
"sbdio",
#ifdef notyet
"apbus",
@@ -152,7 +153,7 @@
if (have_fb_sbdio)
platform.sbdiodevs = tr2a_sbdiodevs;
- ipl_sr_bits = tr2a_sr_bits;
+ ipl_sr_map = tr2a_ipl_sr_map;
kseg2iobufsize = 0x02000000; /* 32MB for APbus and framebuffer */
@@ -171,7 +172,7 @@
tr2a_cache_config(void)
{
- mips_sdcache_size = 1024 * 1024; /* 1MB L2-cache */
+ mips_cache_info.mci_sdcache_size = 1024 * 1024; /* 1MB L2-cache */
}
void
Index: src/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c
diff -u src/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c:1.12 src/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c:1.13
--- src/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c:1.12 Mon Apr 28 20:23:18 2008
+++ src/sys/arch/ews4800mips/ews4800mips/tr2a_intr.c Sun Feb 20 07:55:20 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: tr2a_intr.c,v 1.12 2008/04/28 20:23:18 martin Exp $ */
+/* $NetBSD: tr2a_intr.c,v 1.13 2011/02/20 07:55:20 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@@ -30,12 +30,15 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tr2a_intr.c,v 1.12 2008/04/28 20:23:18 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tr2a_intr.c,v 1.13 2011/02/20 07:55:20 matt Exp $");
+#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/evcnt.h>
+#include <sys/lwp.h>
+#include <sys/cpu.h>
#include <sys/intr.h>
#include <machine/locore.h> /* mips3_cp0* */
@@ -45,27 +48,16 @@
SBD_DECL(tr2a);
-const uint32_t tr2a_sr_bits[_IPL_N] = {
+const struct ipl_sr_map tr2a_ipl_sr_map = {
+ .sr_bits = {
[IPL_NONE] = 0,
- [IPL_SOFTCLOCK] =
- MIPS_SOFT_INT_MASK_0,
- [IPL_SOFTNET] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
- [IPL_VM] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_3 |
- MIPS_INT_MASK_4,
- [IPL_SCHED] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_3 |
- MIPS_INT_MASK_4 |
- MIPS_INT_MASK_5,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_INT_MASK & ~MIPS_INT_MASK_5,
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
+ },
};
#define NIRQ 16
@@ -178,134 +170,124 @@
}
void
-tr2a_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+tr2a_intr(int ppl, vaddr_t pc, uint32_t status)
{
struct tr2a_intr_handler *ih;
struct clockframe cf;
- uint32_t r, intc_cause, handled;
+ uint32_t r, intc_cause, ipending;
+ int ipl;
- handled = 0;
intc_cause = *INTC_STATUS_REG & *INTC_MASK_REG;
- if ((ipending & MIPS_INT_MASK_5) && (intc_cause & INTC_INT5)) {
- cf.pc = pc;
- cf.sr = status;
- tr2a_wbflush();
- *INTC_CLEAR_REG = 0x7c;
- *INTC_STATUS_REG;
-
- hardclock(&cf);
- timer_tr2a_ev.ev_count++;
- handled |= MIPS_INT_MASK_5;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
-
+ while (ppl < (ipl = splintr(&ipending))) {
+ if ((ipending & MIPS_INT_MASK_5) && (intc_cause & INTC_INT5)) {
+ cf.pc = pc;
+ cf.sr = status;
+ cf.intr = (curcpu()->ci_idepth > 0);
+ tr2a_wbflush();
+ *INTC_CLEAR_REG = 0x7c;
+ *INTC_STATUS_REG;
- if ((ipending & MIPS_INT_MASK_4) && (intc_cause & INTC_INT4)) {
- /* KBD, MOUSE, SERIAL */
- r = *ASO_INT_STATUS_REG;
- if (r & 0x300010) {
- ih = &tr2a_intr_handler[4];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
- }
- } else if (r & 0x40) {
- /* kbms */
- ih = &tr2a_intr_handler[9];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
- }
- } else if (r & 0x20) {
- printf("INT4 (1)\n");
- } else if (r & 0x00800000) {
- printf("INT4 (2)\n");
- } else if (r & 0x00400000) {
- printf("INT4 (3)\n");
- } else if (r != 0) {
- printf("not for INT4 %x\n", r);
+ hardclock(&cf);
+ timer_tr2a_ev.ev_count++;
}
- tr2a_wbflush();
- *INTC_CLEAR_REG = 0x68;
- *INTC_STATUS_REG;
+ if ((ipending & MIPS_INT_MASK_4) && (intc_cause & INTC_INT4)) {
+ /* KBD, MOUSE, SERIAL */
+ r = *ASO_INT_STATUS_REG;
+ if (r & 0x300010) {
+ ih = &tr2a_intr_handler[4];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ } else if (r & 0x40) {
+ /* kbms */
+ ih = &tr2a_intr_handler[9];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ } else if (r & 0x20) {
+ printf("INT4 (1)\n");
+ } else if (r & 0x00800000) {
+ printf("INT4 (2)\n");
+ } else if (r & 0x00400000) {
+ printf("INT4 (3)\n");
+ } else if (r != 0) {
+ printf("not for INT4 %x\n", r);
+ }
- handled |= MIPS_INT_MASK_4;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
+ tr2a_wbflush();
+ *INTC_CLEAR_REG = 0x68;
+ *INTC_STATUS_REG;
+ }
- if ((ipending & MIPS_INT_MASK_3) && (intc_cause & INTC_INT3)) {
- /* APbus HI */
- printf("APbus HI\n");
- tr2a_wbflush();
- *INTC_CLEAR_REG = 0x54;
- *INTC_STATUS_REG;
- handled |= MIPS_INT_MASK_3;
- }
+ if ((ipending & MIPS_INT_MASK_3) && (intc_cause & INTC_INT3)) {
+ /* APbus HI */
+ printf("APbus HI\n");
+ tr2a_wbflush();
+ *INTC_CLEAR_REG = 0x54;
+ *INTC_STATUS_REG;
+ }
- if ((ipending & MIPS_INT_MASK_2) && (intc_cause & INTC_INT2)) {
- /* SCSI, ETHER */
- r = *ASO_INT_STATUS_REG;
- if (r & 0x100) { /* SCSI-A */
- ih = &tr2a_intr_handler[6];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
+ if ((ipending & MIPS_INT_MASK_2) && (intc_cause & INTC_INT2)) {
+ /* SCSI, ETHER */
+ r = *ASO_INT_STATUS_REG;
+ if (r & 0x100) { /* SCSI-A */
+ ih = &tr2a_intr_handler[6];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ } else if (r & 0x200) { /* SCSI-B */
+ ih = &tr2a_intr_handler[10];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ } else if (r & 0x1) { /* LANCE */
+ ih = &tr2a_intr_handler[0];
+ if (ih->func) {
+ ih->func(ih->arg);
+ ih->evcnt.ev_count++;
+ }
+ } else if (r != 0) {
+ printf("not for INT2 %x %x\n", r,
+ *ASO_DMAINT_STATUS_REG);
}
- } else if (r & 0x200) { /* SCSI-B */
- ih = &tr2a_intr_handler[10];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
- }
- } else if (r & 0x1) { /* LANCE */
- ih = &tr2a_intr_handler[0];
- if (ih->func) {
- ih->func(ih->arg);
- ih->evcnt.ev_count++;
- }
- } else if (r != 0) {
- printf("not for INT2 %x %x\n", r,
- *ASO_DMAINT_STATUS_REG);
- }
- tr2a_wbflush();
- *INTC_CLEAR_REG = 0x40;
- *INTC_STATUS_REG;
- handled |= MIPS_INT_MASK_2;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
+ tr2a_wbflush();
+ *INTC_CLEAR_REG = 0x40;
+ *INTC_STATUS_REG;
+ }
- if ((ipending & MIPS_INT_MASK_1) && (intc_cause & INTC_INT1)) {
- /* APbus LO */
- printf("APbus LO\n");
- tr2a_wbflush();
- *INTC_CLEAR_REG = 0x2c;
- *INTC_STATUS_REG;
- handled |= MIPS_INT_MASK_1;
- }
+ if ((ipending & MIPS_INT_MASK_1) && (intc_cause & INTC_INT1)) {
+ /* APbus LO */
+ printf("APbus LO\n");
+ tr2a_wbflush();
+ *INTC_CLEAR_REG = 0x2c;
+ *INTC_STATUS_REG;
+ }
- if ((ipending & MIPS_INT_MASK_0) && (intc_cause & INTC_INT0)) {
- /* NMI etc. */
- r = *ASO_INT_STATUS_REG;
- printf("INT0 %08x\n", r);
- if (r & 0x8000) {
- printf("INT0(1) NMI\n");
- } else if (r & 0x8) {
- printf("INT0(2)\n");
- } else if (r & 0x4) {
- printf("INT0(3)\n");
- } else if (r != 0) {
- printf("not for INT0 %x\n", r);
+ if ((ipending & MIPS_INT_MASK_0) && (intc_cause & INTC_INT0)) {
+ /* NMI etc. */
+ r = *ASO_INT_STATUS_REG;
+ printf("INT0 %08x\n", r);
+ if (r & 0x8000) {
+ printf("INT0(1) NMI\n");
+ } else if (r & 0x8) {
+ printf("INT0(2)\n");
+ } else if (r & 0x4) {
+ printf("INT0(3)\n");
+ } else if (r != 0) {
+ printf("not for INT0 %x\n", r);
+ }
+ tr2a_wbflush();
+ *INTC_CLEAR_REG = 0x14;
+ *INTC_STATUS_REG;
}
- tr2a_wbflush();
- *INTC_CLEAR_REG = 0x14;
- *INTC_STATUS_REG;
- handled |= MIPS_INT_MASK_0;
}
- cause &= ~handled;
- _splset(((status & ~cause) & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
}
void
Index: src/sys/arch/ews4800mips/include/intr.h
diff -u src/sys/arch/ews4800mips/include/intr.h:1.10 src/sys/arch/ews4800mips/include/intr.h:1.11
--- src/sys/arch/ews4800mips/include/intr.h:1.10 Mon Apr 28 20:23:18 2008
+++ src/sys/arch/ews4800mips/include/intr.h Sun Feb 20 07:55:21 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.10 2008/04/28 20:23:18 martin Exp $ */
+/* $NetBSD: intr.h,v 1.11 2011/02/20 07:55:21 matt Exp $ */
/*-
* Copyright (c) 2000, 2001, 2004 The NetBSD Foundation, Inc.
@@ -32,59 +32,18 @@
#ifndef _EWS4800MIPS_INTR_H_
#define _EWS4800MIPS_INTR_H_
-#define IPL_NONE 0 /* disable only this interrupt */
-#define IPL_SOFTCLOCK 1 /* clock software interrupts (SI 0) */
-#define IPL_SOFTBIO 1 /* bio software interrupts (SI 0) */
-#define IPL_SOFTNET 2 /* network software interrupts (SI 1) */
-#define IPL_SOFTSERIAL 2 /* serial software interrupts (SI 1) */
-#define IPL_VM 3
-#define IPL_SCHED 4 /* disable clock interrupts */
-#define IPL_HIGH 4 /* disable all interrupts */
-
-#define _IPL_N 5
-
-#define _IPL_SI0_FIRST IPL_SOFTCLOCK
-#define _IPL_SI0_LAST IPL_SOFTBIO
-
-#define _IPL_SI1_FIRST IPL_SOFTNET
-#define _IPL_SI1_LAST IPL_SOFTSERIAL
-
-#define IST_UNUSABLE -1 /* interrupt cannot be used */
-#define IST_NONE 0 /* none (dummy) */
-#define IST_PULSE 1 /* pulsed */
-#define IST_EDGE 2 /* edge-triggered */
-#define IST_LEVEL 3 /* level-triggered */
-
-#include <mips/locore.h>
-
-extern const uint32_t *ipl_sr_bits;
-
-#define spl0() (void) _spllower(0)
-#define splx(s) (void) _splset(s)
-
-typedef int ipl_t;
-typedef struct {
- ipl_t _sr;
-} ipl_cookie_t;
-
-static inline ipl_cookie_t
-makeiplcookie(ipl_t ipl)
-{
-
- return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
-}
-
-static inline int
-splraiseipl(ipl_cookie_t icookie)
-{
-
- return _splraise(icookie._sr);
-}
-
-#include <sys/spl.h>
+#include <mips/intr.h>
+#ifdef _KERNEL
void intr_init(void);
void intr_establish(int, int (*)(void *), void *);
void intr_disestablish(void *);
+#ifdef __INTR_PRIVATE
+extern const struct ipl_sr_map tr2_ipl_sr_map;
+extern const struct ipl_sr_map tr2a_ipl_sr_map;
+#endif
+
+#endif
+
#endif /* !_EWS4800MIPS_INTR_H_ */
Index: src/sys/arch/ews4800mips/include/sbdvar.h
diff -u src/sys/arch/ews4800mips/include/sbdvar.h:1.5 src/sys/arch/ews4800mips/include/sbdvar.h:1.6
--- src/sys/arch/ews4800mips/include/sbdvar.h:1.5 Mon Dec 14 00:46:03 2009
+++ src/sys/arch/ews4800mips/include/sbdvar.h Sun Feb 20 07:55:21 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: sbdvar.h,v 1.5 2009/12/14 00:46:03 matt Exp $ */
+/* $NetBSD: sbdvar.h,v 1.6 2011/02/20 07:55:21 matt Exp $ */
/*-
* Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
@@ -47,7 +47,7 @@
int cpu_clock;
/* mainbus node table */
- const char **mainbusdevs;
+ const char * const *mainbusdevs;
/* System Board I/O device table */
const struct sbdiodevdesc *sbdiodevs;
@@ -68,7 +68,7 @@
void (*intr_init)(void);
void *(*intr_establish)(int, int (*)(void *), void *);
void (*intr_disestablish)(void *);
- void (*intr)(uint32_t, uint32_t, vaddr_t, uint32_t);
+ void (*intr)(int, vaddr_t, uint32_t);
/* Interval timer helper routines */
void (*initclocks)(void);
@@ -88,14 +88,13 @@
void x ## _intr_init(void); \
void *x ## _intr_establish(int, int (*)(void *), void *); \
void x ## _intr_disestablish(void *); \
-void x ## _intr(uint32_t, uint32_t, vaddr_t, uint32_t); \
+void x ## _intr(int, vaddr_t, uint32_t); \
void x ## _initclocks(void); \
void x ## _consinit(void); \
int x ## _ipl_bootdev(void); \
void x ## _reboot(void); \
void x ## _poweroff(void); \
void x ## _ether_addr(uint8_t *); \
-extern const uint32_t x ## _sr_bits[]
#define _SBD_OPS_SET(m, x) platform . x = m ## _ ## x
