Module Name: src
Committed By: matt
Date: Sun Feb 3 15:57:25 UTC 2013
Modified Files:
src/sys/arch/arm/arm32: arm32_machdep.c cpu.c
Log Message:
Add a machdep.cpu_arch sysctl
To generate a diff of this commit:
cvs rdiff -u -r1.91 -r1.92 src/sys/arch/arm/arm32/arm32_machdep.c
cvs rdiff -u -r1.92 -r1.93 src/sys/arch/arm/arm32/cpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/arm32_machdep.c
diff -u src/sys/arch/arm/arm32/arm32_machdep.c:1.91 src/sys/arch/arm/arm32/arm32_machdep.c:1.92
--- src/sys/arch/arm/arm32/arm32_machdep.c:1.91 Thu Jan 31 22:34:26 2013
+++ src/sys/arch/arm/arm32/arm32_machdep.c Sun Feb 3 15:57:09 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: arm32_machdep.c,v 1.91 2013/01/31 22:34:26 matt Exp $ */
+/* $NetBSD: arm32_machdep.c,v 1.92 2013/02/03 15:57:09 matt Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@@ -42,7 +42,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.91 2013/01/31 22:34:26 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.92 2013/02/03 15:57:09 matt Exp $");
#include "opt_modular.h"
#include "opt_md.h"
@@ -101,6 +101,8 @@ int cpu_fpu_present;
int cpu_neon_present;
int cpu_simd_present;
int cpu_simdex_present;
+int cpu_umull_present;
+const char *cpu_arch = "";
int cpu_instruction_set_attributes[6];
int cpu_memory_model_features[4];
@@ -315,6 +317,15 @@ sysctl_machdep_booted_kernel(SYSCTLFN_AR
}
static int
+sysctl_machdep_cpu_arch(SYSCTLFN_ARGS)
+{
+ struct sysctlnode node = *rnode;
+ node.sysctl_data = __UNCONST(cpu_arch);
+ node.sysctl_size = strlen(cpu_arch) + 1;
+ return sysctl_lookup(SYSCTLFN_CALL(&node));
+}
+
+static int
sysctl_machdep_powersave(SYSCTLFN_ARGS)
{
struct sysctlnode node = *rnode;
@@ -365,6 +376,11 @@ SYSCTL_SETUP(sysctl_machdep_setup, "sysc
sysctl_consdev, 0, NULL, sizeof(dev_t),
CTL_MACHDEP, CPU_CONSDEV, CTL_EOL);
sysctl_createv(clog, 0, NULL, NULL,
+ CTLFLAG_PERMANENT,
+ CTLTYPE_STRING, "cpu_arch", NULL,
+ sysctl_machdep_cpu_arch, 0, NULL, 0,
+ CTL_MACHDEP, CTL_CREATE, CTL_EOL);
+ sysctl_createv(clog, 0, NULL, NULL,
CTLFLAG_PERMANENT|CTLFLAG_READWRITE,
CTLTYPE_INT, "powersave", NULL,
sysctl_machdep_powersave, 0, &cpu_do_powersave, 0,
Index: src/sys/arch/arm/arm32/cpu.c
diff -u src/sys/arch/arm/arm32/cpu.c:1.92 src/sys/arch/arm/arm32/cpu.c:1.93
--- src/sys/arch/arm/arm32/cpu.c:1.92 Thu Jan 31 22:34:26 2013
+++ src/sys/arch/arm/arm32/cpu.c Sun Feb 3 15:57:23 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.92 2013/01/31 22:34:26 matt Exp $ */
+/* $NetBSD: cpu.c,v 1.93 2013/02/03 15:57:23 matt Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.92 2013/01/31 22:34:26 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.93 2013/02/03 15:57:23 matt Exp $");
#include <sys/systm.h>
#include <sys/conf.h>
@@ -61,6 +61,7 @@ __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.92
#include <arm/undefined.h>
char cpu_model[256];
+extern const char *cpu_arch;
#ifdef MULTIPROCESSOR
volatile u_int arm_cpu_hatched = 0;
@@ -329,161 +330,164 @@ struct cpuidtab {
enum cpu_class cpu_class;
const char *cpu_classname;
const char * const *cpu_steppings;
+ char cpu_arch[8];
};
const struct cpuidtab cpuids[] = {
{ CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2",
- generic_steppings },
+ generic_steppings, "2" },
{ CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250",
- generic_steppings },
+ generic_steppings, "2" },
{ CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3",
- generic_steppings },
+ generic_steppings, "2A" },
{ CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600",
- generic_steppings },
+ generic_steppings, "3" },
{ CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610",
- generic_steppings },
+ generic_steppings, "3" },
{ CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620",
- generic_steppings },
+ generic_steppings, "3" },
{ CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700",
- generic_steppings },
+ generic_steppings, "3" },
{ CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710",
- generic_steppings },
+ generic_steppings, "3" },
{ CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500",
- generic_steppings },
+ generic_steppings, "3" },
{ CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a",
- generic_steppings },
+ generic_steppings, "3" },
{ CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE",
- generic_steppings },
+ generic_steppings, "3" },
+
+ { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810",
+ generic_steppings, "4" },
+
+ { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110",
+ sa110_steppings, "4" },
+ { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100",
+ sa1100_steppings, "4" },
+ { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110",
+ sa1110_steppings, "4" },
+
+ { CPU_ID_FA526, CPU_CLASS_ARMV4, "FA526",
+ generic_steppings, "4" },
+
+ { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200",
+ ixp12x0_steppings, "4" },
+
{ CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T",
- generic_steppings },
+ generic_steppings, "4T" },
{ CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T",
- generic_steppings },
+ generic_steppings, "4T" },
{ CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)",
- generic_steppings },
+ generic_steppings, "4T" },
{ CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)",
- generic_steppings },
-
- { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810",
- generic_steppings },
-
+ generic_steppings, "4T" },
{ CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T",
- generic_steppings },
+ generic_steppings, "4T" },
{ CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T",
- generic_steppings },
- { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S",
- generic_steppings },
+ generic_steppings, "4T" },
{ CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T",
- generic_steppings },
+ generic_steppings, "4T" },
+ { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T",
+ generic_steppings, "4T" },
+
{ CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S",
- generic_steppings },
+ generic_steppings, "5TE" },
{ CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S",
- generic_steppings },
+ generic_steppings, "5TE" },
{ CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S",
- generic_steppings },
- { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T",
- generic_steppings },
+ generic_steppings, "5TE" },
{ CPU_ID_MV88SV131, CPU_CLASS_ARM9ES, "Sheeva 88SV131",
- generic_steppings },
+ generic_steppings, "5TE" },
{ CPU_ID_MV88FR571_VD, CPU_CLASS_ARM9ES, "Sheeva 88FR571-vd",
- generic_steppings },
-
- { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E",
- generic_steppings },
- { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S",
- generic_steppings },
- { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S",
- generic_steppings },
-
- { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110",
- sa110_steppings },
- { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100",
- sa1100_steppings },
- { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110",
- sa1110_steppings },
-
- { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200",
- ixp12x0_steppings },
+ generic_steppings, "5TE" },
{ CPU_ID_80200, CPU_CLASS_XSCALE, "i80200",
- xscale_steppings },
+ xscale_steppings, "5TE" },
{ CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz",
- i80321_steppings },
+ i80321_steppings, "5TE" },
{ CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz",
- i80321_steppings },
+ i80321_steppings, "5TE" },
{ CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz",
- i80321_steppings },
+ i80321_steppings, "5TE" },
{ CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz",
- i80321_steppings },
+ i80321_steppings, "5TE" },
{ CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz",
- i80219_steppings },
+ i80219_steppings, "5TE" },
{ CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz",
- i80219_steppings },
+ i80219_steppings, "5TE" },
{ CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x",
- pxa27x_steppings },
+ pxa27x_steppings, "5TE" },
{ CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250",
- pxa2x0_steppings },
+ pxa2x0_steppings, "5TE" },
{ CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210",
- pxa2x0_steppings },
+ pxa2x0_steppings, "5TE" },
{ CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250",
- pxa2x0_steppings },
+ pxa2x0_steppings, "5TE" },
{ CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210",
- pxa2x0_steppings },
+ pxa2x0_steppings, "5TE" },
{ CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255/26x",
- pxa255_steppings },
+ pxa255_steppings, "5TE" },
{ CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210",
- pxa2x0_steppings },
+ pxa2x0_steppings, "5TE" },
{ CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz",
- ixp425_steppings },
+ ixp425_steppings, "5TE" },
{ CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz",
- ixp425_steppings },
+ ixp425_steppings, "5TE" },
{ CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz",
- ixp425_steppings },
+ ixp425_steppings, "5TE" },
+
+ { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E",
+ generic_steppings, "5TE" },
+ { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S",
+ generic_steppings, "5TE" },
+
+ { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S",
+ generic_steppings, "5TEJ" },
+ { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S",
+ generic_steppings, "5TEJ" },
{ CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S r0",
- pN_steppings },
+ pN_steppings, "6J" },
{ CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S r1",
- pN_steppings },
+ pN_steppings, "6J" },
#if 0
/* The ARM1156T2-S only has a memory protection unit */
{ CPU_ID_ARM1156T2S, CPU_CLASS_ARM11J, "ARM1156T2-S r0",
- pN_steppings },
+ pN_steppings, "6T2" },
#endif
{ CPU_ID_ARM1176JZS, CPU_CLASS_ARM11J, "ARM1176JZ-S r0",
- pN_steppings },
+ pN_steppings, "6ZK" },
{ CPU_ID_ARM11MPCORE, CPU_CLASS_ARM11J, "ARM11 MPCore",
- generic_steppings },
+ generic_steppings, "6K" },
{ CPU_ID_CORTEXA5R0, CPU_CLASS_CORTEX, "Cortex-A5 r0",
- pN_steppings },
+ pN_steppings, "7A" },
{ CPU_ID_CORTEXA8R1, CPU_CLASS_CORTEX, "Cortex-A8 r1",
- pN_steppings },
+ pN_steppings, "7A" },
{ CPU_ID_CORTEXA8R2, CPU_CLASS_CORTEX, "Cortex-A8 r2",
- pN_steppings },
+ pN_steppings, "7A" },
{ CPU_ID_CORTEXA8R3, CPU_CLASS_CORTEX, "Cortex-A8 r3",
- pN_steppings },
+ pN_steppings, "7A" },
{ CPU_ID_CORTEXA9R2, CPU_CLASS_CORTEX, "Cortex-A9 r2",
- pN_steppings },
+ pN_steppings, "7A" },
{ CPU_ID_CORTEXA9R3, CPU_CLASS_CORTEX, "Cortex-A9 r3",
- pN_steppings },
+ pN_steppings, "7A" },
{ CPU_ID_CORTEXA9R4, CPU_CLASS_CORTEX, "Cortex-A9 r4",
- pN_steppings },
+ pN_steppings, "7A" },
{ CPU_ID_CORTEXA15R2, CPU_CLASS_CORTEX, "Cortex-A15 r2",
- pN_steppings },
+ pN_steppings, "7A" },
{ CPU_ID_CORTEXA15R3, CPU_CLASS_CORTEX, "Cortex-A15 r3",
- pN_steppings },
-
- { CPU_ID_FA526, CPU_CLASS_ARMV4, "FA526",
- generic_steppings },
+ pN_steppings, "7A" },
- { 0, CPU_CLASS_NONE, NULL, NULL }
+ { 0, CPU_CLASS_NONE, NULL, NULL, "" }
};
struct cpu_classtab {
@@ -573,13 +577,15 @@ identify_arm_cpu(device_t dv, struct cpu
for (i = 0; cpuids[i].cpuid != 0; i++)
if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) {
cpu_class = cpuids[i].cpu_class;
+ cpu_arch = cpuids[i].cpu_arch;
steppingstr = cpuids[i].cpu_steppings[cpuid &
CPU_ID_REVISION_MASK];
snprintf(cpu_model, sizeof(cpu_model),
- "%s%s%s (%s core)", cpuids[i].cpu_classname,
+ "%s%s%s (%s V%s core)", cpuids[i].cpu_classname,
steppingstr[0] == '*' ? "" : " ",
&steppingstr[steppingstr[0] == '*'],
- cpu_classes[cpu_class].class_name);
+ cpu_classes[cpu_class].class_name,
+ cpu_arch);
break;
}
