Module Name: src
Committed By: rkujawa
Date: Wed May 29 20:47:14 UTC 2013
Modified Files:
src/sys/arch/arm/marvell: mvsoc.c mvsoc_intr.c mvsoc_space.c mvsocreg.h
mvsocvar.h
Log Message:
Add support for mvsoc-based Armada XP peripherals.
Obtained from Marvell, Semihalf.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/marvell/mvsoc.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/marvell/mvsoc_intr.c \
src/sys/arch/arm/marvell/mvsoc_space.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/marvell/mvsocreg.h \
src/sys/arch/arm/marvell/mvsocvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/marvell/mvsoc.c
diff -u src/sys/arch/arm/marvell/mvsoc.c:1.10 src/sys/arch/arm/marvell/mvsoc.c:1.11
--- src/sys/arch/arm/marvell/mvsoc.c:1.10 Fri Oct 19 06:14:44 2012
+++ src/sys/arch/arm/marvell/mvsoc.c Wed May 29 20:47:14 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsoc.c,v 1.10 2012/10/19 06:14:44 msaitoh Exp $ */
+/* $NetBSD: mvsoc.c,v 1.11 2013/05/29 20:47:14 rkujawa Exp $ */
/*
* Copyright (c) 2007, 2008 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.10 2012/10/19 06:14:44 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.11 2013/05/29 20:47:14 rkujawa Exp $");
#include "opt_cputypes.h"
#include "opt_mvsoc.h"
@@ -46,6 +46,11 @@ __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.
#include <arm/marvell/orionreg.h>
#include <arm/marvell/kirkwoodreg.h>
+#if defined(ARMADAXP)
+#include <evbarm/armadaxp/armadaxpreg.h>
+#include <evbarm/marvell/marvellreg.h>
+#endif
+
#include "locators.h"
#ifdef MVSOC_CONSOLE_EARLY
@@ -64,6 +69,9 @@ uint32_t mvPclk, mvSysclk, mvTclk = 0;
int nwindow = 0, nremap = 0;
static vaddr_t regbase = 0xffffffff, dsc_base, pex_base;
vaddr_t mlmb_base;
+#if defined(ARMADAXP)
+vaddr_t misc_base;
+#endif
void (*mvsoc_intr_init)(void);
@@ -175,8 +183,38 @@ static struct {
{ KIRKWOOD_TAG_CRYPT,
KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT },
#endif
+#if defined(ARMADAXP)
+ { ARMADAXP_TAG_PEX00_MEM,
+ ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX0 },
+ { ARMADAXP_TAG_PEX00_IO,
+ ARMADAXP_ATTR_PEXx0_IO, ARMADAXP_UNITID_PEX0 },
+ { ARMADAXP_TAG_PEX01_MEM,
+ ARMADAXP_ATTR_PEXx1_MEM, ARMADAXP_UNITID_PEX0 },
+ { ARMADAXP_TAG_PEX01_IO,
+ ARMADAXP_ATTR_PEXx1_IO, ARMADAXP_UNITID_PEX0 },
+ { ARMADAXP_TAG_PEX02_MEM,
+ ARMADAXP_ATTR_PEXx2_MEM, ARMADAXP_UNITID_PEX0 },
+ { ARMADAXP_TAG_PEX02_IO,
+ ARMADAXP_ATTR_PEXx2_IO, ARMADAXP_UNITID_PEX0 },
+ { ARMADAXP_TAG_PEX03_MEM,
+ ARMADAXP_ATTR_PEXx3_MEM, ARMADAXP_UNITID_PEX0 },
+ { ARMADAXP_TAG_PEX03_IO,
+ ARMADAXP_ATTR_PEXx3_IO, ARMADAXP_UNITID_PEX0 },
+ { ARMADAXP_TAG_PEX2_MEM,
+ ARMADAXP_ATTR_PEX2_MEM, ARMADAXP_UNITID_PEX2 },
+ { ARMADAXP_TAG_PEX2_IO,
+ ARMADAXP_ATTR_PEX2_IO, ARMADAXP_UNITID_PEX2 },
+ { ARMADAXP_TAG_PEX3_MEM,
+ ARMADAXP_ATTR_PEX3_MEM, ARMADAXP_UNITID_PEX3 },
+ { ARMADAXP_TAG_PEX3_IO,
+ ARMADAXP_ATTR_PEX3_IO, ARMADAXP_UNITID_PEX3 },
+#endif
};
+#if defined(ARMADAXP)
+#undef ARMADAXP
+#define ARMADAXP(m) MARVELL_ARMADAXP_ ## m
+#endif
#if defined(ORION)
#define ORION_1(m) MARVELL_ORION_1_ ## m
#define ORION_2(m) MARVELL_ORION_2_ ## m
@@ -242,6 +280,15 @@ static struct {
{ MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" },
{ MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" },
#endif
+
+#if defined(ARMADAXP)
+ { ARMADAXP(MV78130), 1, "MV78130", "A0", "Armada XP" },
+ { ARMADAXP(MV78160), 1, "MV78160", "A0", "Armada XP" },
+ { ARMADAXP(MV78230), 1, "MV78260", "A0", "Armada XP" },
+ { ARMADAXP(MV78260), 1, "MV78260", "A0", "Armada XP" },
+ { ARMADAXP(MV78460), 1, "MV78460", "A0", "Armada XP" },
+ { ARMADAXP(MV78460), 2, "MV78460", "B0", "Armada XP" },
+#endif
};
#define OFFSET_DEFAULT MVA_OFFSET_DEFAULT
@@ -445,6 +492,83 @@ static const struct mvsoc_periph {
{ MV78XX0(MV78200), "gttwsi",0,MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI },
:
#endif
+
+#if defined(ARMADAXP)
+ { ARMADAXP(MV78130), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 },
+ { ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0INT },
+ { ARMADAXP(MV78130), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1INT },
+ { ARMADAXP(MV78130), "com", 2, ARMADAXP_COM2_BASE, ARMADAXP_IRQ_UART2INT },
+ { ARMADAXP(MV78130), "com", 3, ARMADAXP_COM3_BASE, ARMADAXP_IRQ_UART3INT },
+ { ARMADAXP(MV78130), "mvsocrtc",0, ARMADAXP_RTC_BASE, ARMADAXP_IRQ_RTCINT },
+ { ARMADAXP(MV78130), "ehci", 0, ARMADAXP_USB0_BASE, ARMADAXP_IRQ_USB0INT },
+ { ARMADAXP(MV78130), "ehci", 1, ARMADAXP_USB1_BASE, ARMADAXP_IRQ_USB1INT },
+ { ARMADAXP(MV78130), "mvpex", 0, ARMADAXP_PEX00_BASE, ARMADAXP_IRQ_PEX00},
+ { ARMADAXP(MV78130), "mvpex", 1, ARMADAXP_PEX01_BASE, ARMADAXP_IRQ_PEX01},
+ { ARMADAXP(MV78130), "mvpex", 2, ARMADAXP_PEX02_BASE, ARMADAXP_IRQ_PEX02},
+ { ARMADAXP(MV78130), "mvpex", 3, ARMADAXP_PEX03_BASE, ARMADAXP_IRQ_PEX03},
+
+ { ARMADAXP(MV78160), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 },
+ { ARMADAXP(MV78160), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0INT },
+ { ARMADAXP(MV78160), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1INT },
+ { ARMADAXP(MV78160), "com", 2, ARMADAXP_COM2_BASE, ARMADAXP_IRQ_UART2INT },
+ { ARMADAXP(MV78160), "com", 3, ARMADAXP_COM3_BASE, ARMADAXP_IRQ_UART3INT },
+ { ARMADAXP(MV78160), "mvsocrtc",0, ARMADAXP_RTC_BASE, ARMADAXP_IRQ_RTCINT },
+ { ARMADAXP(MV78160), "ehci", 0, ARMADAXP_USB0_BASE, ARMADAXP_IRQ_USB0INT },
+ { ARMADAXP(MV78160), "ehci", 1, ARMADAXP_USB1_BASE, ARMADAXP_IRQ_USB1INT },
+ { ARMADAXP(MV78160), "mvpex", 0, ARMADAXP_PEX00_BASE, ARMADAXP_IRQ_PEX00},
+ { ARMADAXP(MV78160), "mvpex", 1, ARMADAXP_PEX01_BASE, ARMADAXP_IRQ_PEX01},
+ { ARMADAXP(MV78160), "mvpex", 2, ARMADAXP_PEX02_BASE, ARMADAXP_IRQ_PEX02},
+ { ARMADAXP(MV78160), "mvpex", 3, ARMADAXP_PEX03_BASE, ARMADAXP_IRQ_PEX03},
+ { ARMADAXP(MV78160), "mvpex", 4, ARMADAXP_PEX2_BASE, ARMADAXP_IRQ_PEX2},
+
+ { ARMADAXP(MV78230), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 },
+ { ARMADAXP(MV78230), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0INT },
+ { ARMADAXP(MV78230), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1INT },
+ { ARMADAXP(MV78230), "com", 2, ARMADAXP_COM2_BASE, ARMADAXP_IRQ_UART2INT },
+ { ARMADAXP(MV78230), "com", 3, ARMADAXP_COM3_BASE, ARMADAXP_IRQ_UART3INT },
+ { ARMADAXP(MV78230), "mvsocrtc",0, ARMADAXP_RTC_BASE, ARMADAXP_IRQ_RTCINT },
+ { ARMADAXP(MV78230), "ehci", 0, ARMADAXP_USB0_BASE, ARMADAXP_IRQ_USB0INT },
+ { ARMADAXP(MV78230), "ehci", 1, ARMADAXP_USB1_BASE, ARMADAXP_IRQ_USB1INT },
+ { ARMADAXP(MV78230), "mvpex", 0, ARMADAXP_PEX00_BASE, ARMADAXP_IRQ_PEX00},
+ { ARMADAXP(MV78230), "mvpex", 1, ARMADAXP_PEX01_BASE, ARMADAXP_IRQ_PEX01},
+ { ARMADAXP(MV78230), "mvpex", 2, ARMADAXP_PEX02_BASE, ARMADAXP_IRQ_PEX02},
+ { ARMADAXP(MV78230), "mvpex", 3, ARMADAXP_PEX03_BASE, ARMADAXP_IRQ_PEX03},
+ { ARMADAXP(MV78230), "mvpex", 4, ARMADAXP_PEX2_BASE, ARMADAXP_IRQ_PEX2},
+
+ { ARMADAXP(MV78260), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 },
+ { ARMADAXP(MV78260), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0INT },
+ { ARMADAXP(MV78260), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1INT },
+ { ARMADAXP(MV78260), "com", 2, ARMADAXP_COM2_BASE, ARMADAXP_IRQ_UART2INT },
+ { ARMADAXP(MV78260), "com", 3, ARMADAXP_COM3_BASE, ARMADAXP_IRQ_UART3INT },
+ { ARMADAXP(MV78260), "mvsocrtc",0, ARMADAXP_RTC_BASE, ARMADAXP_IRQ_RTCINT },
+ { ARMADAXP(MV78260), "ehci", 0, ARMADAXP_USB0_BASE, ARMADAXP_IRQ_USB0INT },
+ { ARMADAXP(MV78260), "ehci", 1, ARMADAXP_USB1_BASE, ARMADAXP_IRQ_USB1INT },
+ { ARMADAXP(MV78260), "mvpex", 0, ARMADAXP_PEX00_BASE, ARMADAXP_IRQ_PEX00},
+ { ARMADAXP(MV78260), "mvpex", 1, ARMADAXP_PEX01_BASE, ARMADAXP_IRQ_PEX01},
+ { ARMADAXP(MV78260), "mvpex", 2, ARMADAXP_PEX02_BASE, ARMADAXP_IRQ_PEX02},
+ { ARMADAXP(MV78260), "mvpex", 3, ARMADAXP_PEX03_BASE, ARMADAXP_IRQ_PEX03},
+ { ARMADAXP(MV78260), "mvpex", 4, ARMADAXP_PEX2_BASE, ARMADAXP_IRQ_PEX2},
+
+ { ARMADAXP(MV78460), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 },
+ { ARMADAXP(MV78460), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0INT },
+ { ARMADAXP(MV78460), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1INT },
+ { ARMADAXP(MV78460), "com", 2, ARMADAXP_COM2_BASE, ARMADAXP_IRQ_UART2INT },
+ { ARMADAXP(MV78460), "com", 3, ARMADAXP_COM3_BASE, ARMADAXP_IRQ_UART3INT },
+ { ARMADAXP(MV78460), "mvsocrtc",0, ARMADAXP_RTC_BASE, ARMADAXP_IRQ_RTCINT },
+ { ARMADAXP(MV78460), "ehci", 0, ARMADAXP_USB0_BASE, ARMADAXP_IRQ_USB0INT },
+ { ARMADAXP(MV78460), "ehci", 1, ARMADAXP_USB1_BASE, ARMADAXP_IRQ_USB1INT },
+ { ARMADAXP(MV78460), "mvpex", 0, ARMADAXP_PEX00_BASE, ARMADAXP_IRQ_PEX00},
+ { ARMADAXP(MV78460), "mvpex", 1, ARMADAXP_PEX01_BASE, ARMADAXP_IRQ_PEX01},
+ { ARMADAXP(MV78460), "mvpex", 2, ARMADAXP_PEX02_BASE, ARMADAXP_IRQ_PEX02},
+ { ARMADAXP(MV78460), "mvpex", 3, ARMADAXP_PEX03_BASE, ARMADAXP_IRQ_PEX03},
+ { ARMADAXP(MV78460), "mvpex", 4, ARMADAXP_PEX2_BASE, ARMADAXP_IRQ_PEX2},
+ { ARMADAXP(MV78460), "mvpex", 5, ARMADAXP_PEX3_BASE, ARMADAXP_IRQ_PEX3},
+ { ARMADAXP(MV78460), "mvsata", 0, ARMADAXP_SATAHC_BASE, ARMADAXP_IRQ_SATA0 },
+ { ARMADAXP(MV78460), "gttwsi", 0, ARMADAXP_TWSI0_BASE, ARMADAXP_IRQ_TWSI0},
+ { ARMADAXP(MV78460), "gttwsi", 1, ARMADAXP_TWSI1_BASE, ARMADAXP_IRQ_TWSI1},
+ { ARMADAXP(MV78460), "mvspi", 0, ARMADAXP_SPI0_BASE, ARMADAXP_IRQ_SPI0},
+ { ARMADAXP(MV78460), "mvspi", 1, ARMADAXP_SPI1_BASE, ARMADAXP_IRQ_SPI0},
+#endif
};
@@ -594,7 +718,12 @@ void
mvsoc_bootstrap(bus_addr_t iobase)
{
+#if defined(ARMADAXP)
+ regbase = MARVELL_INTERREGS_PBASE;
+ misc_base = iobase + MVSOC_MISC_BASE;
+#else
regbase = iobase;
+#endif
dsc_base = iobase + MVSOC_DSC_BASE;
mlmb_base = iobase + MVSOC_MLMB_BASE;
pex_base = iobase + MVSOC_PEX_BASE;
Index: src/sys/arch/arm/marvell/mvsoc_intr.c
diff -u src/sys/arch/arm/marvell/mvsoc_intr.c:1.5 src/sys/arch/arm/marvell/mvsoc_intr.c:1.6
--- src/sys/arch/arm/marvell/mvsoc_intr.c:1.5 Sun Jul 29 00:07:10 2012
+++ src/sys/arch/arm/marvell/mvsoc_intr.c Wed May 29 20:47:14 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsoc_intr.c,v 1.5 2012/07/29 00:07:10 matt Exp $ */
+/* $NetBSD: mvsoc_intr.c,v 1.6 2013/05/29 20:47:14 rkujawa Exp $ */
/*
* Copyright (c) 2010 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mvsoc_intr.c,v 1.5 2012/07/29 00:07:10 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mvsoc_intr.c,v 1.6 2013/05/29 20:47:14 rkujawa Exp $");
#define _INTR_PRIVATE
@@ -40,6 +40,12 @@ __KERNEL_RCSID(0, "$NetBSD: mvsoc_intr.c
#include <arm/marvell/mvsocreg.h>
#include <arm/marvell/mvsocvar.h>
+#include "opt_mvsoc.h"
+
+#if defined(ARMADAXP)
+extern void armadaxp_handle_irq(void *);
+#endif
+
int (*find_pending_irqs)(void);
static void mvsoc_bridge_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
@@ -74,6 +80,10 @@ void
mvsoc_irq_handler(void *frame)
{
struct cpu_info * const ci = curcpu();
+#if defined(ARMADAXP)
+ ci->ci_data.cpu_nintr++;
+ armadaxp_handle_irq(frame);
+#else
const int oldipl = ci->ci_cpl;
const uint32_t oldipl_mask = __BIT(oldipl);
int ipl_mask = 0;
@@ -87,6 +97,7 @@ mvsoc_irq_handler(void *frame)
*/
if ((ipl_mask & ~oldipl_mask) > oldipl_mask)
pic_do_pending_ints(I32_bit, oldipl, frame);
+#endif
}
/*
Index: src/sys/arch/arm/marvell/mvsoc_space.c
diff -u src/sys/arch/arm/marvell/mvsoc_space.c:1.5 src/sys/arch/arm/marvell/mvsoc_space.c:1.6
--- src/sys/arch/arm/marvell/mvsoc_space.c:1.5 Sat Jul 28 23:13:16 2012
+++ src/sys/arch/arm/marvell/mvsoc_space.c Wed May 29 20:47:14 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsoc_space.c,v 1.5 2012/07/28 23:13:16 matt Exp $ */
+/* $NetBSD: mvsoc_space.c,v 1.6 2013/05/29 20:47:14 rkujawa Exp $ */
/*
* Copyright (c) 2007 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mvsoc_space.c,v 1.5 2012/07/28 23:13:16 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mvsoc_space.c,v 1.6 2013/05/29 20:47:14 rkujawa Exp $");
#include "opt_mvsoc.h"
#include "mvpex.h"
@@ -214,6 +214,81 @@ struct bus_space kirkwood_pex1_io_bs_tag
#endif
};
#endif
+
+#if defined(ARMADAXP)
+struct bus_space armadaxp_pex00_mem_bs_tag = {
+ /* cookie */
+ (void *)ARMADAXP_TAG_PEX00_MEM,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space armadaxp_pex00_io_bs_tag = {
+ /* cookie */
+ (void *)ARMADAXP_TAG_PEX00_IO,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space armadaxp_pex01_mem_bs_tag = {
+ /* cookie */
+ (void *)ARMADAXP_TAG_PEX01_MEM,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space armadaxp_pex01_io_bs_tag = {
+ /* cookie */
+ (void *)ARMADAXP_TAG_PEX01_IO,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space armadaxp_pex02_mem_bs_tag = {
+ /* cookie */
+ (void *)ARMADAXP_TAG_PEX02_MEM,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space armadaxp_pex02_io_bs_tag = {
+ /* cookie */
+ (void *)ARMADAXP_TAG_PEX02_IO,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space armadaxp_pex03_mem_bs_tag = {
+ /* cookie */
+ (void *)ARMADAXP_TAG_PEX03_MEM,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space armadaxp_pex03_io_bs_tag = {
+ /* cookie */
+ (void *)ARMADAXP_TAG_PEX03_IO,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space armadaxp_pex2_mem_bs_tag = {
+ /* cookie */
+ (void *)ARMADAXP_TAG_PEX2_MEM,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space armadaxp_pex2_io_bs_tag = {
+ /* cookie */
+ (void *)ARMADAXP_TAG_PEX2_IO,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space armadaxp_pex3_mem_bs_tag = {
+ /* cookie */
+ (void *)ARMADAXP_TAG_PEX3_MEM,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space armadaxp_pex3_io_bs_tag = {
+ /* cookie */
+ (void *)ARMADAXP_TAG_PEX3_IO,
+
+ MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+#endif
#endif
#if NGTPCI > 0
@@ -248,6 +323,14 @@ mvsoc_bs_map(void *space, bus_addr_t add
paddr_t startpa, endpa, offset, pa;
pt_entry_t *pte;
vaddr_t va;
+
+/*
+ * XXX: We are not configuring any decode windows for Armada XP
+ * at the moment. We rely on those that have been set by u-boot.
+ * Hence we don't want to mess around with decode windows,
+ * till we get full controll over them.
+ */
+
int tag = (int)space;
if (tag != 0) {
Index: src/sys/arch/arm/marvell/mvsocreg.h
diff -u src/sys/arch/arm/marvell/mvsocreg.h:1.3 src/sys/arch/arm/marvell/mvsocreg.h:1.4
--- src/sys/arch/arm/marvell/mvsocreg.h:1.3 Fri Oct 19 06:14:44 2012
+++ src/sys/arch/arm/marvell/mvsocreg.h Wed May 29 20:47:14 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsocreg.h,v 1.3 2012/10/19 06:14:44 msaitoh Exp $ */
+/* $NetBSD: mvsocreg.h,v 1.4 2013/05/29 20:47:14 rkujawa Exp $ */
/*
* Copyright (c) 2007, 2008 KIYOHARA Takashi
* All rights reserved.
@@ -55,6 +55,11 @@
#define MVSOC_DSC_CSSR_WINEN 0x00000001
#define MVSOC_DSC_CSSR_SIZE_MASK 0xff000000
+/*
+ * SoC MISC Register
+ */
+
+#define MVSOC_MISC_BASE (MVSOC_DEVBUS_BASE + 0x8200) /* For Armada XP */
/*
* Device Bus
@@ -84,13 +89,23 @@
#define MVSOC_MLMB_BASE (UNITID2PHYS(MLMB)) /* 0x20000 */
/* CPU Address Map Registers */
+#if defined(ARMADAXP)
+#define MVSOC_MLMB_WCR(w) ((w) < 8 ? ((w) << 4) + 0x0 :\
+ (((w) - 8) << 3) + 0x90)
+#else
#define MVSOC_MLMB_WCR(w) (((w) << 4) + 0x0)
+#endif
#define MVSOC_MLMB_WCR_WINEN (1 << 0)
#define MVSOC_MLMB_WCR_TARGET(t) (((t) & 0xf) << 4)
#define MVSOC_MLMB_WCR_ATTR(a) (((a) & 0xff) << 8)
#define MVSOC_MLMB_WCR_SIZE_MASK 0xffff0000
#define MVSOC_MLMB_WCR_SIZE(s) (((s) - 1) & MVSOC_MLMB_WCR_SIZE_MASK)
+#if defined(ARMADAXP)
+#define MVSOC_MLMB_WBR(w) ((w) < 8 ? ((w) << 4) + 0x4 :\
+ (((w) - 8) << 3) + 0x94)
+#else
#define MVSOC_MLMB_WBR(w) (((w) << 4) + 0x4)
+#endif
#define MVSOC_MLMB_WBR_BASE_MASK 0xffff0000
#define MVSOC_MLMB_WRLR(w) (((w) << 4) + 0x8)
#define MVSOC_MLMB_WRLR_REMAP_MASK 0xffff0000
@@ -101,11 +116,17 @@
/* CPU Control and Status Registers */
#define MVSOC_MLMB_CPUCR 0x100 /* CPU Configuration Register */
#define MVSOC_MLMB_CPUCSR 0x104 /* CPU Control/Status Register*/
+#if defined(ARMADAXP)
+#define MVSOC_MLMB_RSTOUTNMASKR 0x60 /* RSTOUTn Mask Register */
+#define MVSOC_MLMB_SSRR 0x64 /* System Soft Reset Register */
+#define MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN (1 << 0)
+#else
#define MVSOC_MLMB_RSTOUTNMASKR 0x108 /* RSTOUTn Mask Register */
+#define MVSOC_MLMB_SSRR 0x10c /* System Soft Reset Register */
+#define MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN (1 << 2)
+#endif
#define MVSOC_MLMB_RSTOUTNMASKR_PEXRSTOUTEN (1 << 0)
#define MVSOC_MLMB_RSTOUTNMASKR_WDRSTOUTEN (1 << 1)
-#define MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN (1 << 2)
-#define MVSOC_MLMB_SSRR 0x10c /* System Soft Reset Register */
#define MVSOC_MLMB_SSRR_SYSTEMSOFTRST (1 << 0)
#define MVSOC_MLMB_MLMBICR 0x110 /*Mb-L to Mb Bridge Intr Cause*/
#define MVSOC_MLMB_MLMBIMR 0x114 /*Mb-L to Mb Bridge Intr Mask */
@@ -115,6 +136,13 @@
#define MVSOC_MLMB_L2CFG 0x128 /* L2 Cache Config */
+/* Coherent Fabric Control and Status */
+#define MVSOC_MLMB_COHERENCY_FABRIC_CTRL 0x200
+#define MVSOC_MLMB_COHERENCY_FABRIC_CFG 0x204
+
+/* CIB registers offsets */
+#define MVSOC_MLMB_CIB_CTRL_CFG 0x280
+
#define MVSOC_TMR_BASE (MVSOC_MLMB_BASE + 0x0300)
/* CPU Doorbell Registers */
Index: src/sys/arch/arm/marvell/mvsocvar.h
diff -u src/sys/arch/arm/marvell/mvsocvar.h:1.3 src/sys/arch/arm/marvell/mvsocvar.h:1.4
--- src/sys/arch/arm/marvell/mvsocvar.h:1.3 Wed Jul 18 09:45:58 2012
+++ src/sys/arch/arm/marvell/mvsocvar.h Wed May 29 20:47:14 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsocvar.h,v 1.3 2012/07/18 09:45:58 kiyohara Exp $ */
+/* $NetBSD: mvsocvar.h,v 1.4 2013/05/29 20:47:14 rkujawa Exp $ */
/*
* Copyright (c) 2007, 2010 KIYOHARA Takashi
* All rights reserved.
@@ -47,6 +47,11 @@ extern int nwindow, nremap;
extern int gpp_npins, gpp_irqbase;
extern struct bus_space mvsoc_bs_tag;
extern struct arm32_bus_dma_tag mvsoc_bus_dma_tag;
+#if defined(ARMADAXP)
+extern vaddr_t misc_base;
+#define read_miscreg(o) (*(volatile uint32_t *)(misc_base + (o)))
+#define write_miscreg(o, v) (*(volatile uint32_t *)(misc_base + (o)) = (v))
+#endif
#define read_mlmbreg(o) (*(volatile uint32_t *)(mlmb_base + (o)))
#define write_mlmbreg(o, v) (*(volatile uint32_t *)(mlmb_base + (o)) = (v))
@@ -82,9 +87,25 @@ enum mvsoc_tags {
KIRKWOOD_TAG_SPI,
KIRKWOOD_TAG_BOOTROM,
KIRKWOOD_TAG_CRYPT,
+
+ ARMADAXP_TAG_PEX00_MEM,
+ ARMADAXP_TAG_PEX00_IO,
+ ARMADAXP_TAG_PEX01_MEM,
+ ARMADAXP_TAG_PEX01_IO,
+ ARMADAXP_TAG_PEX02_MEM,
+ ARMADAXP_TAG_PEX02_IO,
+ ARMADAXP_TAG_PEX03_MEM,
+ ARMADAXP_TAG_PEX03_IO,
+ ARMADAXP_TAG_PEX2_MEM,
+ ARMADAXP_TAG_PEX2_IO,
+ ARMADAXP_TAG_PEX3_MEM,
+ ARMADAXP_TAG_PEX3_IO,
};
int mvsoc_target(int, uint32_t *, uint32_t *, uint32_t *, uint32_t *);
+void armadaxp_getclks(void);
+void armadaxp_intr_bootstrap(void);
+
void orion_intr_bootstrap(void);
void orion_getclks(bus_addr_t);
