Module Name: src
Committed By: dsl
Date: Sun Dec 8 18:00:51 UTC 2013
Modified Files:
src/sys/arch/amd64/amd64: cpufunc.S
src/sys/arch/x86/include: cpufunc.h specialreg.h
Log Message:
Add some definitions for cpu 'extended state'.
These are needed for support of the AVX SIMD instructions.
Nothing yet uses them.
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/amd64/amd64/cpufunc.S
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/x86/include/cpufunc.h
cvs rdiff -u -r1.73 -r1.74 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/amd64/amd64/cpufunc.S
diff -u src/sys/arch/amd64/amd64/cpufunc.S:1.21 src/sys/arch/amd64/amd64/cpufunc.S:1.22
--- src/sys/arch/amd64/amd64/cpufunc.S:1.21 Sat Sep 24 21:24:52 2011
+++ src/sys/arch/amd64/amd64/cpufunc.S Sun Dec 8 18:00:51 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.S,v 1.21 2011/09/24 21:24:52 jym Exp $ */
+/* $NetBSD: cpufunc.S,v 1.22 2013/12/08 18:00:51 dsl Exp $ */
/*-
* Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
@@ -244,6 +244,21 @@ ENTRY(rdmsr_safe)
movq %rax, PCB_ONFAULT(%r8)
ret
+ENTRY(rdxcr)
+ movq %rdi, %rcx
+ xgetbv
+ shlq $32, %rdx
+ orq %rdx, %rax
+ ret
+
+ENTRY(wrxcr)
+ movq %rdi, %rcx
+ movq %rsi, %rax
+ movq %rsi, %rdx
+ shrq $32, %rdx
+ xsetbv
+ ret
+
/*
* MSR operations fault handler
*/
@@ -468,6 +483,27 @@ ENTRY(fldummy)
flds (%rdi)
ret
+ENTRY(xsave)
+ movq %rsi, %rax
+ movq %rsi, %rdx
+ shrq $32, %rdx
+ xsave (%rdi)
+ ret
+
+ENTRY(xsaveopt)
+ movq %rsi, %rax
+ movq %rsi, %rdx
+ shrq $32, %rdx
+ xsaveopt (%rdi)
+ ret
+
+ENTRY(xrstor)
+ movq %rsi, %rax
+ movq %rsi, %rdx
+ shrq $32, %rdx
+ xrstor (%rdi)
+ ret
+
ENTRY(x86_ldmxcsr)
ldmxcsr (%rdi)
ret
Index: src/sys/arch/x86/include/cpufunc.h
diff -u src/sys/arch/x86/include/cpufunc.h:1.13 src/sys/arch/x86/include/cpufunc.h:1.14
--- src/sys/arch/x86/include/cpufunc.h:1.13 Sat Sep 24 10:32:52 2011
+++ src/sys/arch/x86/include/cpufunc.h Sun Dec 8 18:00:51 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.h,v 1.13 2011/09/24 10:32:52 jym Exp $ */
+/* $NetBSD: cpufunc.h,v 1.14 2013/12/08 18:00:51 dsl Exp $ */
/*-
* Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
@@ -93,8 +93,9 @@ void fxrstor(void *);
void x86_monitor(const void *, uint32_t, uint32_t);
void x86_mwait(uint32_t, uint32_t);
void x86_ldmxcsr(void *);
+/* x86_cpuid2() writes four 32bit values, %eax, %ebx, %ecx and %edx */
#define x86_cpuid(a,b) x86_cpuid2((a),0,(b))
-void x86_cpuid2(unsigned, unsigned, unsigned *);
+void x86_cpuid2(uint32_t, uint32_t, uint32_t *);
/* Use read_psl, write_psl when saving and restoring interrupt state. */
void x86_disable_intr(void);
@@ -126,6 +127,14 @@ void wrmsr_locked(u_int, u_int, uint64_
void setfs(int);
void setusergs(int);
+/* Extended processor state functions (for AVX registers etc) */
+
+uint64_t rdxcr(uint32_t); /* xgetbv */
+void wrxcr(uint32_t, uint64_t); /* xsetgv */
+void xrstor(const void *, uint64_t);
+void xsave(void *, uint64_t);
+void xsaveopt(const void *, uint64_t);
+
#endif /* _KERNEL */
#endif /* !_X86_CPUFUNC_H_ */
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.73 src/sys/arch/x86/include/specialreg.h:1.74
--- src/sys/arch/x86/include/specialreg.h:1.73 Wed Nov 20 17:50:39 2013
+++ src/sys/arch/x86/include/specialreg.h Sun Dec 8 18:00:51 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.73 2013/11/20 17:50:39 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.74 2013/12/08 18:00:51 dsl Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -218,6 +218,39 @@
? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4)))
/*
+ * Extended Control Register XCR0
+ */
+#define XCR0_X87 0x00000001 /* x87 FPU/MMX state */
+#define XCR0_SSE 0x00000002 /* SSE state */
+#define XCR0_AVX 0x00000004 /* AVX state (ymmn registers) */
+
+#define XCR0_FLAGS1 "\20" \
+ "\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "B03"
+
+/*
+ * CPUID Processor extended state Enumeration Fn0000000d
+ *
+ * %ecx == 0: supported features info:
+ * %edx:%eax bits valid for XCR0
+ * %ebx Save area size for features enabled in XCR0
+ * %ecx Maximim save area size for all cpu features
+ *
+ * %ecx == 1:
+ * %eax: Bit 0 => xsaveopt instruction avalaible (sandy bridge onwards)
+ *
+ * %ecx >= 2: Save area details for XCR0 bit n
+ * %eax: size of save area for this feature
+ * %ebx: offset of save area for this feature
+ * %ecx, %edx: reserved
+ * All of %eax, %ebx, %ecx and %edx are zero for unsupported features.
+ */
+
+#define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */
+
+#define CPUID_PES1_FLAGS "\20" \
+ "\1" "XSAVEOPT"
+
+/*
* Intel Deterministic Cache Parameter Leaf
* Fn0000_0004
*/
