Module Name: src
Committed By: kiyohara
Date: Mon Dec 23 03:19:43 UTC 2013
Modified Files:
src/sys/arch/arm/marvell: armadaxp.c armadaxpreg.h mvsoc.c mvsocreg.h
mvsocvar.h
src/sys/arch/evbarm/armadaxp: armadaxp_machdep.c
src/sys/arch/evbarm/marvell: marvell_machdep.c
Log Message:
Move Misc Registers from mvsocreg.h to armadaxpreg.h. These registers only
Armada XP. The misc_base initializes in initarm() instead of mvsoc_bootstrap().
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/marvell/armadaxp.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/marvell/armadaxpreg.h
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/marvell/mvsoc.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/marvell/mvsocreg.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/marvell/mvsocvar.h
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/evbarm/marvell/marvell_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/marvell/armadaxp.c
diff -u src/sys/arch/arm/marvell/armadaxp.c:1.4 src/sys/arch/arm/marvell/armadaxp.c:1.5
--- src/sys/arch/arm/marvell/armadaxp.c:1.4 Wed Nov 20 12:16:47 2013
+++ src/sys/arch/arm/marvell/armadaxp.c Mon Dec 23 03:19:43 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp.c,v 1.4 2013/11/20 12:16:47 kiyohara Exp $ */
+/* $NetBSD: armadaxp.c,v 1.5 2013/12/23 03:19:43 kiyohara Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
*******************************************************************************/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.4 2013/11/20 12:16:47 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.5 2013/12/23 03:19:43 kiyohara Exp $");
#define _INTR_PRIVATE
@@ -84,6 +84,8 @@ bus_space_handle_t mpic_cpu_handle;
static bus_space_handle_t mpic_handle, l2_handle;
int l2cache_state = 0;
int iocc_state = 0;
+#define read_miscreg(r) (*(volatile uint32_t *)(misc_base + (r)))
+vaddr_t misc_base;
extern void (*mvsoc_intr_init)(void);
static void armadaxp_intr_init(void);
Index: src/sys/arch/arm/marvell/armadaxpreg.h
diff -u src/sys/arch/arm/marvell/armadaxpreg.h:1.1 src/sys/arch/arm/marvell/armadaxpreg.h:1.2
--- src/sys/arch/arm/marvell/armadaxpreg.h:1.1 Mon Sep 30 13:33:05 2013
+++ src/sys/arch/arm/marvell/armadaxpreg.h Mon Dec 23 03:19:43 2013
@@ -180,10 +180,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#define ARMADAXP_PMU_BASE (MVSOC_DEVBUS_BASE + 0xc000)
/*
- * SoC MISC Registers
+ * Miscellanseous Register
*/
+#define ARMADAXP_MISC_BASE (MVSOC_DEVBUS_BASE + 0x8200)
+
+#define ARMADAXP_MISC_PMCGC 0x20 /* PM Clock Gating Control */
#define ARMADAXP_MISC_SAR_LO 0x30 /* Sample At Reset Low */
#define ARMADAXP_MISC_SAR_HI 0x34 /* Sample At Reset High */
+#define ARMADAXP_MISC_RSTOUTNMASKR 0x60 /* RSTOUTn Mask Register */
+#define ARMADAXP_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN (1 << 0)
+#define ARMADAXP_MISC_SSRR 0x64 /* System Soft Reset Register */
+#define ARMADAXP_MISC_SSRR_GLOBALSOFTRST (1 << 0)
/* Multiprocessor Interrupt Controller Registers */
#define ARMADAXP_MLMB_MPIC_BASE 0x20a00
Index: src/sys/arch/arm/marvell/mvsoc.c
diff -u src/sys/arch/arm/marvell/mvsoc.c:1.14 src/sys/arch/arm/marvell/mvsoc.c:1.15
--- src/sys/arch/arm/marvell/mvsoc.c:1.14 Mon Dec 23 02:52:47 2013
+++ src/sys/arch/arm/marvell/mvsoc.c Mon Dec 23 03:19:43 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsoc.c,v 1.14 2013/12/23 02:52:47 kiyohara Exp $ */
+/* $NetBSD: mvsoc.c,v 1.15 2013/12/23 03:19:43 kiyohara Exp $ */
/*
* Copyright (c) 2007, 2008 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.14 2013/12/23 02:52:47 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.15 2013/12/23 03:19:43 kiyohara Exp $");
#include "opt_cputypes.h"
#include "opt_mvsoc.h"
@@ -67,7 +67,6 @@ static int mvsoc_search(device_t, cfdata
uint32_t mvPclk, mvSysclk, mvTclk = 0;
int nwindow = 0, nremap = 0;
static vaddr_t regbase = 0xffffffff, dsc_base, pex_base;
-vaddr_t misc_base;
vaddr_t mlmb_base;
void (*mvsoc_intr_init)(void);
@@ -846,7 +845,6 @@ mvsoc_bootstrap(bus_addr_t iobase)
regbase = iobase;
dsc_base = iobase + MVSOC_DSC_BASE;
- misc_base = iobase + MVSOC_MISC_BASE;
mlmb_base = iobase + MVSOC_MLMB_BASE;
pex_base = iobase + MVSOC_PEX_BASE;
#ifdef MVSOC_CONSOLE_EARLY
Index: src/sys/arch/arm/marvell/mvsocreg.h
diff -u src/sys/arch/arm/marvell/mvsocreg.h:1.6 src/sys/arch/arm/marvell/mvsocreg.h:1.7
--- src/sys/arch/arm/marvell/mvsocreg.h:1.6 Wed Nov 20 12:36:16 2013
+++ src/sys/arch/arm/marvell/mvsocreg.h Mon Dec 23 03:19:43 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsocreg.h,v 1.6 2013/11/20 12:36:16 kiyohara Exp $ */
+/* $NetBSD: mvsocreg.h,v 1.7 2013/12/23 03:19:43 kiyohara Exp $ */
/*
* Copyright (c) 2007, 2008 KIYOHARA Takashi
* All rights reserved.
@@ -78,16 +78,6 @@
#define MVSOC_COM1_BASE (MVSOC_DEVBUS_BASE + 0x2100)
/*
- * Miscellanseous Register
- */
-#define MVSOC_MISC_BASE (MVSOC_DEVBUS_BASE + 0x8200) /* For Armada XP */
-
-#define MVSOC_MISC_RSTOUTNMASKR 0x60 /* RSTOUTn Mask Register */
-#define MVSOC_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN (1 << 0)
-#define MVSOC_MISC_SSRR 0x64 /* System Soft Reset Register */
-#define MVSOC_MISC_SSRR_GLOBALSOFTRST (1 << 0)
-
-/*
* Mbus-L to Mbus Bridge Registers
*/
#define MVSOC_MLMB_BASE (UNITID2PHYS(MLMB)) /* 0x20000 */
Index: src/sys/arch/arm/marvell/mvsocvar.h
diff -u src/sys/arch/arm/marvell/mvsocvar.h:1.5 src/sys/arch/arm/marvell/mvsocvar.h:1.6
--- src/sys/arch/arm/marvell/mvsocvar.h:1.5 Mon Sep 30 13:12:56 2013
+++ src/sys/arch/arm/marvell/mvsocvar.h Mon Dec 23 03:19:43 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsocvar.h,v 1.5 2013/09/30 13:12:56 kiyohara Exp $ */
+/* $NetBSD: mvsocvar.h,v 1.6 2013/12/23 03:19:43 kiyohara Exp $ */
/*
* Copyright (c) 2007, 2010 KIYOHARA Takashi
* All rights reserved.
@@ -42,16 +42,12 @@ struct mvsoc_softc {
typedef int (*mvsoc_irq_handler_t)(void *);
extern uint32_t mvPclk, mvSysclk, mvTclk;
-extern vaddr_t misc_base;
extern vaddr_t mlmb_base;
extern int nwindow, nremap;
extern int gpp_npins, gpp_irqbase;
extern struct bus_space mvsoc_bs_tag;
extern struct arm32_bus_dma_tag mvsoc_bus_dma_tag;
-#define read_miscreg(o) (*(volatile uint32_t *)(misc_base + (o)))
-#define write_miscreg(o, v) (*(volatile uint32_t *)(misc_base + (o)) = (v))
-
#define read_mlmbreg(o) (*(volatile uint32_t *)(mlmb_base + (o)))
#define write_mlmbreg(o, v) (*(volatile uint32_t *)(mlmb_base + (o)) = (v))
Index: src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c
diff -u src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c:1.4 src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c:1.5
--- src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c:1.4 Wed Nov 20 12:36:16 2013
+++ src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c Mon Dec 23 03:19:43 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp_machdep.c,v 1.4 2013/11/20 12:36:16 kiyohara Exp $ */
+/* $NetBSD: armadaxp_machdep.c,v 1.5 2013/12/23 03:19:43 kiyohara Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
*******************************************************************************/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp_machdep.c,v 1.4 2013/11/20 12:36:16 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp_machdep.c,v 1.5 2013/12/23 03:19:43 kiyohara Exp $");
#include "opt_machdep.h"
#include "opt_mvsoc.h"
@@ -163,13 +163,17 @@ static void axp_device_register(device_t
static void
axp_system_reset(void)
{
+ extern vaddr_t misc_base;
+
+#define write_miscreg(r, v) (*(volatile uint32_t *)(misc_base + (r)) = (v))
+
cpu_reset_address = 0;
/* Unmask soft reset */
- write_miscreg(MVSOC_MISC_RSTOUTNMASKR,
- MVSOC_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN);
+ write_miscreg(ARMADAXP_MISC_RSTOUTNMASKR,
+ ARMADAXP_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN);
/* Assert soft reset */
- write_miscreg(MVSOC_MISC_SSRR, MVSOC_MISC_SSRR_GLOBALSOFTRST);
+ write_miscreg(ARMADAXP_MISC_SSRR, ARMADAXP_MISC_SSRR_GLOBALSOFTRST);
while (1);
}
@@ -349,6 +353,8 @@ initarm(void *arg)
reset_axp_pcie_win();
/* Get CPU, system and timebase frequencies */
+ extern vaddr_t misc_base;
+ misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE;
armadaxp_getclks();
/* Preconfigure interrupts */
Index: src/sys/arch/evbarm/marvell/marvell_machdep.c
diff -u src/sys/arch/evbarm/marvell/marvell_machdep.c:1.24 src/sys/arch/evbarm/marvell/marvell_machdep.c:1.25
--- src/sys/arch/evbarm/marvell/marvell_machdep.c:1.24 Wed Nov 20 12:59:21 2013
+++ src/sys/arch/evbarm/marvell/marvell_machdep.c Mon Dec 23 03:19:43 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: marvell_machdep.c,v 1.24 2013/11/20 12:59:21 kiyohara Exp $ */
+/* $NetBSD: marvell_machdep.c,v 1.25 2013/12/23 03:19:43 kiyohara Exp $ */
/*
* Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi
* All rights reserved.
@@ -25,7 +25,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.24 2013/11/20 12:59:21 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.25 2013/12/23 03:19:43 kiyohara Exp $");
#include "opt_evbarm_boardtype.h"
#include "opt_ddb.h"
@@ -134,7 +134,7 @@ static void marvell_startend_by_tag(int,
#if defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0)
static void
-marvell_system_reset_old(void)
+marvell_system_reset(void)
{
/* unmask soft reset */
write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR,
@@ -152,14 +152,17 @@ marvell_system_reset_old(void)
#if defined(ARMADAXP)
static void
-marvell_system_reset(void)
+armadaxp_system_reset(void)
{
+ extern vaddr_t misc_base;
+
+#define write_miscreg(r, v) (*(volatile uint32_t *)(misc_base + (r)) = (v))
/* Unmask soft reset */
- write_miscreg(MVSOC_MISC_RSTOUTNMASKR,
- MVSOC_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN);
+ write_miscreg(ARMADAXP_MISC_RSTOUTNMASKR,
+ ARMADAXP_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN);
/* Assert soft reset */
- write_miscreg(MVSOC_MISC_SSRR, MVSOC_MISC_SSRR_GLOBALSOFTRST);
+ write_miscreg(ARMADAXP_MISC_SSRR, ARMADAXP_MISC_SSRR_GLOBALSOFTRST);
while (1);
@@ -283,7 +286,7 @@ initarm(void *arg)
case MARVELL_ORION_1_88W8660:
case MARVELL_ORION_2_88F1281:
case MARVELL_ORION_2_88F5281:
- cpu_reset_address = marvell_system_reset_old;
+ cpu_reset_address = marvell_system_reset;
orion_intr_bootstrap();
@@ -301,7 +304,7 @@ initarm(void *arg)
case MARVELL_KIRKWOOD_88F6192:
case MARVELL_KIRKWOOD_88F6281:
case MARVELL_KIRKWOOD_88F6282:
- cpu_reset_address = marvell_system_reset_old;
+ cpu_reset_address = marvell_system_reset;
kirkwood_intr_bootstrap();
@@ -317,7 +320,7 @@ initarm(void *arg)
#ifdef MV78XX0
case MARVELL_MV78XX0_MV78100:
case MARVELL_MV78XX0_MV78200:
- cpu_reset_address = marvell_system_reset_old;
+ cpu_reset_address = marvell_system_reset;
mv78xx0_intr_bootstrap();
@@ -336,7 +339,7 @@ initarm(void *arg)
case MARVELL_ARMADAXP_MV78230:
case MARVELL_ARMADAXP_MV78260:
case MARVELL_ARMADAXP_MV78460:
- cpu_reset_address = marvell_system_reset;
+ cpu_reset_address = armadaxp_system_reset;
armadaxp_intr_bootstrap(MARVELL_INTERREGS_PBASE);
@@ -345,6 +348,8 @@ initarm(void *arg)
nwindow = ARMADAXP_MLMB_NWINDOW;
nremap = ARMADAXP_MLMB_NREMAP;
+ extern vaddr_t misc_base;
+ misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE;
armadaxp_getclks();
#ifdef L2CACHE_ENABLE
@@ -355,7 +360,7 @@ initarm(void *arg)
(void)armadaxp_l2_init(MARVELL_INTERREGS_PBASE);
}
#endif
-
+
#ifdef AURORA_IO_CACHE_COHERENCY
/* Initialize cache coherency */
armadaxp_io_coherency_init();
@@ -469,7 +474,7 @@ consinit(void)
extern int mvuart_cnattach(bus_space_tag_t, bus_addr_t, int,
uint32_t, int);
- if (mvuart_cnattach(&mvsoc_bs_tag,
+ if (mvuart_cnattach(&mvsoc_bs_tag,
MARVELL_INTERREGS_PBASE + MVSOC_COM0_BASE,
comcnspeed, mvTclk, comcnmode))
panic("can't init serial console");
