Module Name: src
Committed By: matt
Date: Wed Dec 18 18:31:22 UTC 2013
Modified Files:
src/gnu/dist/binutils/opcodes [matt-nb5-mips64]: arm-dis.c
Log Message:
Decode some armv7 instructions
To generate a diff of this commit:
cvs rdiff -u -r1.1.1.3 -r1.1.1.3.32.1 src/gnu/dist/binutils/opcodes/arm-dis.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/gnu/dist/binutils/opcodes/arm-dis.c
diff -u src/gnu/dist/binutils/opcodes/arm-dis.c:1.1.1.3 src/gnu/dist/binutils/opcodes/arm-dis.c:1.1.1.3.32.1
--- src/gnu/dist/binutils/opcodes/arm-dis.c:1.1.1.3 Thu Feb 2 21:14:00 2006
+++ src/gnu/dist/binutils/opcodes/arm-dis.c Wed Dec 18 18:31:22 2013
@@ -80,6 +80,7 @@
%A print address for ldc/stc/ldf/stf instruction
%m print register mask for ldm/stm instruction
%C print the PSR sub type.
+ %E print the LSB and WIDTH fields of a BFI or BFC instruction.
%F print the COUNT field of a LFM/SFM instruction.
IWMMXT specific format options:
%<bitfield>g print as an iWMMXt 64-bit register
@@ -118,6 +119,18 @@ static const struct arm_opcode arm_opcod
{ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
{ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
+ /* ARM V7 instructions. */
+ {ARM_EXT_V7A, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
+ {ARM_EXT_V7A, 0x07c0001f, 0x0fa0007f, "bfc%c\t%12-15R, %E"},
+ {ARM_EXT_V7A, 0x07c00010, 0x0fa00070, "bfi%c\t%12-15R, %0-3r, %E"},
+ {ARM_EXT_V7A, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, #%16-19,0-11d"},
+ {ARM_EXT_V7A, 0xf57ff05f, 0xffffffff, "dmb"},
+ {ARM_EXT_V7A, 0xf57ff050, 0xfffffff0, "dmb\t#%0-3d"},
+ {ARM_EXT_V7A, 0xf57ff05f, 0xffffffff, "dsb"},
+ {ARM_EXT_V7A, 0xf57ff050, 0xfffffff0, "dsb\t%#0-3d"},
+ {ARM_EXT_V7A, 0xf57ff06f, 0xffffffff, "isb"},
+ {ARM_EXT_V7A, 0xf57ff060, 0xfffffff0, "isb\t%#0-3d"},
+
/* ARM V6Z instructions. */
{ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smi%c\t%e"},
@@ -380,7 +393,8 @@ static const struct arm_opcode arm_opcod
{ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"},
{ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
{ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
- {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"},
+ {ARM_EXT_V1, 0x01100000, 0x0df00000, "tst%c%p\t%16-19r, %o"},
+ {ARM_EXT_V1, 0x03100000, 0x0df00000, "tst%c%p\t%16-19r, %o"},
{ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"},
{ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"},
{ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"},
@@ -1234,6 +1248,19 @@ print_insn_arm (pc, info, given)
func (stream, "c");
break;
+ case 'E':
+ {
+ long msb = (given >> 16) & 0x1f;
+ long lsb = (given >> 7) & 0x1f;
+ long width = msb - lsb + 1;
+
+ if (width > 0)
+ func(stream, "#%lu, #%lu", lsb, width);
+ else
+ func(stream, "(invalid %lu:%lu)", lsb, msb);
+ }
+ break;
+
case 'F':
switch (given & 0x00408000)
{
@@ -1307,60 +1334,59 @@ print_insn_arm (pc, info, given)
{
int bitstart = *c++ - '0';
int bitend = 0;
+ long value = 0;
+
while (*c >= '0' && *c <= '9')
bitstart = (bitstart * 10) + *c++ - '0';
switch (*c)
{
case '-':
- c++;
+ while (*c == '-')
+ {
+ c++;
+ bitend = 0;
+ while (*c >= '0' && *c <= '9')
+ bitend = (bitend * 10) + *c++ - '0';
- while (*c >= '0' && *c <= '9')
- bitend = (bitend * 10) + *c++ - '0';
+ if (!bitend)
+ abort ();
+
+ if (*c == ',')
+ {
+ c++;
+ value <<= (bitend - bitstart + 1);
+ value |= (given & ((2 << bitend) - 1)) >> bitstart;
+
+ bitstart = 0;
+ while (*c >= '0' && *c <= '9')
+ bitstart = (bitstart * 10) + *c++ - '0';
+ }
+ }
- if (!bitend)
- abort ();
+ value <<= (bitend - bitstart + 1);
+ value |= (given & ((2 << bitend) - 1)) >> bitstart;
switch (*c)
{
case 'r':
{
- long reg;
-
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
-
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, "%s", arm_regnames[value]);
}
break;
case 'd':
{
- long reg;
-
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
-
- func (stream, "%d", reg);
+ func (stream, "%d", value);
}
break;
case 'W':
{
- long reg;
-
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
-
- func (stream, "%d", reg + 1);
+ func (stream, "%d", value + 1);
}
break;
case 'x':
{
- long reg;
-
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
-
- func (stream, "0x%08x", reg);
+ func (stream, "0x%08x", value);
/* Some SWI instructions have special
meanings. */
@@ -1372,44 +1398,31 @@ print_insn_arm (pc, info, given)
break;
case 'X':
{
- long reg;
-
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
-
- func (stream, "%01x", reg & 0xf);
+ func (stream, "%01x", value & 0xf);
}
break;
case 'f':
{
- long reg;
-
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
-
- if (reg > 7)
+ if (value > 7)
func (stream, "#%s",
- arm_fp_const[reg & 7]);
+ arm_fp_const[value & 7]);
else
- func (stream, "f%d", reg);
+ func (stream, "f%d", value);
}
break;
case 'w':
{
- long reg;
-
if (bitstart != bitend)
{
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
if (bitend - bitstart == 1)
- func (stream, "%s", iwmmxt_wwnames[reg]);
+ func (stream, "%s", iwmmxt_wwnames[value]);
else
- func (stream, "%s", iwmmxt_wwssnames[reg]);
+ func (stream, "%s", iwmmxt_wwssnames[value]);
}
else
{
+ long reg;
reg = (((given >> 8) & 0x1) |
((given >> 22) & 0x1));
func (stream, "%s", iwmmxt_wwnames[reg]);
@@ -1419,7 +1432,6 @@ print_insn_arm (pc, info, given)
case 'g':
{
- long reg;
int current_regnames;
if (! iwmmxt_regnames)
@@ -1427,16 +1439,13 @@ print_insn_arm (pc, info, given)
current_regnames = set_arm_regname_option
(iwmmxt_regnames);
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, "%s", arm_regnames[value]);
set_arm_regname_option (current_regnames);
}
break;
case 'G':
{
- long reg;
int current_regnames;
if (! iwmmxt_regnames)
@@ -1444,9 +1453,7 @@ print_insn_arm (pc, info, given)
current_regnames = set_arm_regname_option
(iwmmxt_regnames + 1);
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, "%s", arm_regnames[value]);
set_arm_regname_option (current_regnames);
}
break;
