Module Name: src
Committed By: matt
Date: Sat Jun 6 04:38:52 UTC 2015
Modified Files:
src/sys/arch/mips/mips: db_interface.c
Log Message:
Add octeon mach commands nmi and reset. Teach DDB about Cavium BBIT branch
instructions.
To generate a diff of this commit:
cvs rdiff -u -r1.75 -r1.76 src/sys/arch/mips/mips/db_interface.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/db_interface.c
diff -u src/sys/arch/mips/mips/db_interface.c:1.75 src/sys/arch/mips/mips/db_interface.c:1.76
--- src/sys/arch/mips/mips/db_interface.c:1.75 Thu Aug 18 21:04:23 2011
+++ src/sys/arch/mips/mips/db_interface.c Sat Jun 6 04:38:52 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: db_interface.c,v 1.75 2011/08/18 21:04:23 matt Exp $ */
+/* $NetBSD: db_interface.c,v 1.76 2015/06/06 04:38:52 matt Exp $ */
/*
* Mach Operating System
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.75 2011/08/18 21:04:23 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.76 2015/06/06 04:38:52 matt Exp $");
#include "opt_multiprocessor.h"
#include "opt_cputype.h" /* which mips CPUs do we support? */
@@ -78,7 +78,7 @@ static void db_unwatch_cmd(db_expr_t, bo
#endif /* (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */
#ifdef MULTIPROCESSOR
-static void db_mach_cpu(db_expr_t, bool, db_expr_t, const char *);
+static void db_mach_cpu_cmd(db_expr_t, bool, db_expr_t, const char *);
#endif
void db_tlbdump_cmd(db_expr_t, bool, db_expr_t, const char *);
@@ -129,7 +129,7 @@ kdb_trap(int type, struct reg *regs)
s = splhigh();
-#ifdef MULTIPROCESSOR
+#if defined(MULTIPROCESSOR)
bool first_in_ddb = false;
const u_int cpu_me = cpu_number();
const u_int old_ddb_cpu = atomic_cas_uint(&ddb_cpu, NOCPU, cpu_me);
@@ -155,7 +155,7 @@ kdb_trap(int type, struct reg *regs)
db_active--;
*regs = ddb_regs;
-#ifdef MULTIPROCESSOR
+#if defined(MULTIPROCESSOR)
if (atomic_cas_uint(&ddb_cpu, cpu_me, NOCPU) == cpu_me) {
cpu_resume_others();
} else {
@@ -185,6 +185,18 @@ db_read_bytes(vaddr_t addr, size_t size,
{
const char *src = (char *)addr;
+ if (size <= 8 && (size & (size-1)) == 0 && (addr & (size-1)) == 0
+ && ((uintptr_t)data & (size-1)) == 0) {
+ if (size == sizeof(uint8_t))
+ *(uint8_t *)data = *(const uint8_t *)src;
+ else if (size == sizeof(uint16_t))
+ *(uint16_t *)data = *(const uint16_t *)src;
+ else if (size == sizeof(uint32_t))
+ *(uint32_t *)data = *(const uint32_t *)src;
+ else
+ *(uint64_t *)data = *(const uint64_t *)src;
+ return;
+ }
while (size--)
*data++ = *src++;
}
@@ -198,6 +210,18 @@ db_write_bytes(vaddr_t addr, size_t size
char *p = (char *)addr;
size_t n = size;
+ if (size <= 8 && (size & (size-1)) == 0 && (addr & (size-1)) == 0
+ && ((uintptr_t)data & (size-1)) == 0) {
+ if (size == sizeof(uint8_t))
+ *(uint8_t *)p = *(const uint8_t *)data;
+ else if (size == sizeof(uint16_t))
+ *(uint16_t *)p = *(const uint16_t *)data;
+ else if (size == sizeof(uint32_t))
+ *(uint32_t *)p = *(const uint32_t *)data;
+ else
+ *(uint64_t *)p = *(const uint64_t *)data;
+ return;
+ }
while (n--)
*p++ = *data++;
@@ -706,9 +730,51 @@ db_mtcr_cmd(db_expr_t addr, bool have_ad
}
#endif /* MIPS64_XLS */
+#ifdef MIPS64_OCTEON
+#include <mips/cavium/dev/octeon_ciureg.h>
+
+#ifdef MULTIPROCESSOR
+static void
+db_mach_nmi_cmd(db_expr_t addr, bool have_addr, db_expr_t count,
+ const char *modif)
+{
+ CPU_INFO_ITERATOR cii;
+ struct cpu_info *ci;
+
+ if (!have_addr) {
+ db_printf("CPU not specific\n");
+ return;
+ }
+ for (CPU_INFO_FOREACH(cii, ci)) {
+ if (cpu_index(ci) == addr)
+ break;
+ }
+ if (ci == NULL) {
+ db_printf("CPU %ld not configured\n", (long)addr);
+ return;
+ }
+ if (ci == curcpu()) {
+ db_printf("CPU %ld is current cpu; request ignored\n",
+ (long)addr);
+ return;
+ }
+ mips64_sd_a64(MIPS_PHYS_TO_XKPHYS_UNCACHED(CIU_NMI),
+ __BIT(ci->ci_cpuid));
+}
+#endif
+
+static void
+db_mach_reset_cmd(db_expr_t addr, bool have_addr, db_expr_t count,
+ const char *modif)
+{
+ mips64_sd_a64(MIPS_PHYS_TO_XKPHYS_UNCACHED(CIU_SOFT_RST),
+ mips64_ld_a64(MIPS_PHYS_TO_XKPHYS_UNCACHED(CIU_FUSE)));
+}
+
+#endif
const struct db_command db_machine_command_table[] = {
#ifdef MULTIPROCESSOR
- { DDB_ADD_CMD("cpu", db_mach_cpu, 0,
+ { DDB_ADD_CMD("cpu", db_mach_cpu_cmd, 0,
"switch to another cpu", "cpu#", NULL) },
#endif
{ DDB_ADD_CMD("cp0", db_cp0dump_cmd, 0,
@@ -737,6 +803,16 @@ const struct db_command db_machine_comma
"Set processor control register",
NULL, NULL) },
#endif
+#ifdef MIPS64_OCTEON
+#ifdef MULTIPROCESSOR
+ { DDB_ADD_CMD("nmi", db_mach_nmi_cmd, CS_NOREPEAT,
+ "Send NMI to processor",
+ "cpu#", NULL) },
+#endif
+ { DDB_ADD_CMD("reset", db_mach_reset_cmd, CS_NOREPEAT,
+ "Initiate hardware reset",
+ NULL, NULL) },
+#endif
{ DDB_ADD_CMD(NULL, NULL, 0, NULL,NULL,NULL) }
};
#endif /* !KGDB */
@@ -756,6 +832,12 @@ inst_branch(int inst)
case OP_REGIMM:
case OP_J:
case OP_JAL:
+#if MIPS64_OCTEON
+ case OP_CVM_BBIT0:
+ case OP_CVM_BBIT032:
+ case OP_CVM_BBIT1:
+ case OP_CVM_BBIT132:
+#endif
case OP_BEQ:
case OP_BNE:
case OP_BLEZ:
@@ -934,7 +1016,7 @@ db_resume_others(void)
}
static void
-db_mach_cpu(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
+db_mach_cpu_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
{
CPU_INFO_ITERATOR cii;
struct cpu_info *ci;
