Module Name: src
Committed By: tnn
Date: Sat Aug 8 23:30:16 UTC 2015
Modified Files:
src/sys/arch/arm/allwinner: awin_com.c awin_reg.h
Log Message:
fix attachment of non-console UARTs and ensure the UART clock is running
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/allwinner/awin_com.c
cvs rdiff -u -r1.78 -r1.79 src/sys/arch/arm/allwinner/awin_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_com.c
diff -u src/sys/arch/arm/allwinner/awin_com.c:1.9 src/sys/arch/arm/allwinner/awin_com.c:1.10
--- src/sys/arch/arm/allwinner/awin_com.c:1.9 Sun Dec 7 12:44:24 2014
+++ src/sys/arch/arm/allwinner/awin_com.c Sat Aug 8 23:30:16 2015
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_com.c,v 1.9 2014/12/07 12:44:24 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_com.c,v 1.10 2015/08/08 23:30:16 tnn Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -130,7 +130,28 @@ awin_com_match(device_t parent, cfdata_t
awin_gpio_pinset_acquire(pinset);
bus_space_subregion(iot, aio->aio_core_bsh,
- loc->loc_offset, loc->loc_size, &bsh);
+ loc->loc_offset / 4, loc->loc_size, &bsh);
+
+ /*
+ * Clock gating, soft reset
+ */
+ if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_REG,
+ AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART0 << loc->loc_port, 0);
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_REG,
+ AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART0 << loc->loc_port, 0);
+ } else {
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_APB1_GATING_REG,
+ AWIN_APB_GATING1_UART0 << loc->loc_port, 0);
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_A31_APB2_RESET_REG,
+ AWIN_A31_APB2_RESET_UART0_RST << loc->loc_port, 0);
+ }
+ }
const int rv = comprobe1(iot, bsh);
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.78 src/sys/arch/arm/allwinner/awin_reg.h:1.79
--- src/sys/arch/arm/allwinner/awin_reg.h:1.78 Wed Jun 3 12:22:41 2015
+++ src/sys/arch/arm/allwinner/awin_reg.h Sat Aug 8 23:30:16 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_reg.h,v 1.78 2015/06/03 12:22:41 skrll Exp $ */
+/* $NetBSD: awin_reg.h,v 1.79 2015/08/08 23:30:16 tnn Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -2416,6 +2416,13 @@ struct awin_mmc_idma_descriptor {
#define AWIN_A31_APB1_RESET_DIGITAL_MIC_RST __BIT(4)
#define AWIN_A31_APB1_RESET_CODEC_RST __BIT(0)
+#define AWIN_A31_APB2_RESET_UART5_RST __BIT(21)
+#define AWIN_A31_APB2_RESET_UART4_RST __BIT(20)
+#define AWIN_A31_APB2_RESET_UART3_RST __BIT(19)
+#define AWIN_A31_APB2_RESET_UART2_RST __BIT(18)
+#define AWIN_A31_APB2_RESET_UART1_RST __BIT(17)
+#define AWIN_A31_APB2_RESET_UART0_RST __BIT(16)
+
#define AWIN_A31_APB2_RESET_TWI3_RST __BIT(3)
#define AWIN_A31_APB2_RESET_TWI2_RST __BIT(2)
#define AWIN_A31_APB2_RESET_TWI1_RST __BIT(1)
@@ -2786,6 +2793,13 @@ struct awin_a31_dma_desc {
#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_GMAC __BIT(17)
#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_USB_HOST __BIT(1)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART5 __BIT(21)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART4 __BIT(20)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART3 __BIT(19)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART2 __BIT(18)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART1 __BIT(17)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART0 __BIT(16)
+
#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI4 __BIT(4)
#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI2 __BIT(3)
#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI3 __BIT(2)
@@ -2798,6 +2812,13 @@ struct awin_a31_dma_desc {
#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_GMAC __BIT(17)
#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_USB_DRD __BIT(1)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART5 __BIT(21)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART4 __BIT(20)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART3 __BIT(19)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART2 __BIT(18)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART1 __BIT(17)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART0 __BIT(16)
+
#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI4 __BIT(4)
#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI3 __BIT(3)
#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI2 __BIT(2)
