Module Name: src
Committed By: bouyer
Date: Sat Oct 17 14:46:01 UTC 2015
Modified Files:
src/sys/arch/arm/allwinner: awin_board.c
Log Message:
awin_cpu_clk(): Fix reading of CPU_CLK_SRC_CEL bits: doing a shiftin followed
by a shiftout ends up reading bits(0,1) instead of AWIN_CPU_CLK_SRC_SEL.
It happens that these bits (AWIN_AXI_CLK_DIV_RATIO) are 2 (divide by 3) at boot
(at last on cubieboard2 and olimex lime2), which matches
AWIN_CPU_CLK_SRC_SEL_PLL1, so this has gone unnoticed.
To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/arm/allwinner/awin_board.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_board.c
diff -u src/sys/arch/arm/allwinner/awin_board.c:1.35 src/sys/arch/arm/allwinner/awin_board.c:1.36
--- src/sys/arch/arm/allwinner/awin_board.c:1.35 Mon Apr 20 01:33:22 2015
+++ src/sys/arch/arm/allwinner/awin_board.c Sat Oct 17 14:46:01 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_board.c,v 1.35 2015/04/20 01:33:22 matt Exp $ */
+/* $NetBSD: awin_board.c,v 1.36 2015/10/17 14:46:01 bouyer Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -36,7 +36,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.35 2015/04/20 01:33:22 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.36 2015/10/17 14:46:01 bouyer Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -143,8 +143,7 @@ awin_cpu_clk(void)
AWIN_CPU_AHB_APB0_CFG_REG;
const uint32_t cpu0_cfg = bus_space_read_4(bst, awin_core_bsh,
AWIN_CCM_OFFSET + reg);
- const u_int cpu_clk_sel = __SHIFTIN(cpu0_cfg, AWIN_CPU_CLK_SRC_SEL);
- switch (__SHIFTOUT(cpu_clk_sel, AWIN_CPU_CLK_SRC_SEL)) {
+ switch (__SHIFTOUT(cpu0_cfg, AWIN_CPU_CLK_SRC_SEL)) {
case AWIN_CPU_CLK_SRC_SEL_LOSC:
ci->ci_data.cpu_cc_freq = 32768;
break;
