Module Name: src
Committed By: maya
Date: Wed Mar 7 15:44:15 UTC 2018
Replace early interrupt disable code.
As suggested by dh, carefully disable interrupts before frobbing
interrupt mask, which might trigger more interrupts.
Don't bother with keeping BEV and such.
Note that we are zeroing out STATUS later on in the (NOFPU || emips)
case right now.
This change is risky for emips which wasn't tested and didn't reach
To generate a diff of this commit:
cvs rdiff -u -r1.210 -r1.211 src/sys/arch/mips/mips/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
diff -u src/sys/arch/mips/mips/locore.S:1.210 src/sys/arch/mips/mips/locore.S:1.211
--- src/sys/arch/mips/mips/locore.S:1.210 Wed Jan 24 03:13:36 2018
+++ src/sys/arch/mips/mips/locore.S Wed Mar 7 15:44:15 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.210 2018/01/24 03:13:36 maya Exp $ */
+/* $NetBSD: locore.S,v 1.211 2018/03/07 15:44:15 maya Exp $ */
* Copyright (c) 1992, 1993
@@ -63,7 +63,7 @@
-RCSID("$NetBSD: locore.S,v 1.210 2018/01/24 03:13:36 maya Exp $")
+RCSID("$NetBSD: locore.S,v 1.211 2018/03/07 15:44:15 maya Exp $")
@@ -73,23 +73,18 @@ RCSID("$NetBSD: locore.S,v 1.210 2018/01
.globl _C_LABEL(kernel_text) # libkvm refers this
-#if (defined(MIPS3_PLUS) && !defined(MIPS1)) || defined(emips)
- /* keep firmware exception handler until we hook. */
- mfc0 v0, MIPS_COP_0_STATUS
+ /* First disable the interrupts only, for safety */
+ mfc0 k0, MIPS_COP_0_STATUS
- and v0, MIPS_SR_TS | MIPS3_SR_RE
- and v0, MIPS_SR_BEV
- mtc0 v0, MIPS_COP_0_STATUS # Disable interrupts
- mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts
+ and k0, ~MIPS_SR_INT_IE
+ mtc0 k0, MIPS_COP_0_STATUS
+ /* Known state: BEV, coprocessors disabled */
+ mtc0 zero, MIPS_COP_0_STATUS
mtc0 zero, MIPS_COP_0_CAUSE
// U-boot on the erlite starts all cpus at the kernel entry point.