Module Name: src
Committed By: jmcneill
Date: Tue May 1 19:53:14 UTC 2018
Modified Files:
src/sys/arch/arm/sunxi: files.sunxi
Added Files:
src/sys/arch/arm/sunxi: sun50i_h6_ccu.c sun50i_h6_ccu.h
Log Message:
Add support for Allwinner H6 CCU.
To generate a diff of this commit:
cvs rdiff -u -r1.48 -r1.49 src/sys/arch/arm/sunxi/files.sunxi
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/sunxi/sun50i_h6_ccu.c \
src/sys/arch/arm/sunxi/sun50i_h6_ccu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/sunxi/files.sunxi
diff -u src/sys/arch/arm/sunxi/files.sunxi:1.48 src/sys/arch/arm/sunxi/files.sunxi:1.49
--- src/sys/arch/arm/sunxi/files.sunxi:1.48 Tue Apr 3 12:52:16 2018
+++ src/sys/arch/arm/sunxi/files.sunxi Tue May 1 19:53:14 2018
@@ -1,4 +1,4 @@
-# $NetBSD: files.sunxi,v 1.48 2018/04/03 12:52:16 bouyer Exp $
+# $NetBSD: files.sunxi,v 1.49 2018/05/01 19:53:14 jmcneill Exp $
#
# Configuration info for Allwinner sunxi family SoCs
#
@@ -59,6 +59,11 @@ device sun50ia64ccu: sunxi_ccu
attach sun50ia64ccu at fdt with sunxi_a64_ccu
file arch/arm/sunxi/sun50i_a64_ccu.c sunxi_a64_ccu
+# CCU (H6)
+device sun50ih6ccu: sunxi_ccu
+attach sun50ih6ccu at fdt with sunxi_h6_ccu
+file arch/arm/sunxi/sun50i_h6_ccu.c sunxi_h6_ccu
+
# Misc. clock resets
device sunxiresets
attach sunxiresets at fdt with sunxi_resets
Added files:
Index: src/sys/arch/arm/sunxi/sun50i_h6_ccu.c
diff -u /dev/null src/sys/arch/arm/sunxi/sun50i_h6_ccu.c:1.1
--- /dev/null Tue May 1 19:53:14 2018
+++ src/sys/arch/arm/sunxi/sun50i_h6_ccu.c Tue May 1 19:53:14 2018
@@ -0,0 +1,354 @@
+/* $NetBSD: sun50i_h6_ccu.c,v 1.1 2018/05/01 19:53:14 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2018 Jared McNeill <jmcne...@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: sun50i_h6_ccu.c,v 1.1 2018/05/01 19:53:14 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/sunxi/sunxi_ccu.h>
+#include <arm/sunxi/sun50i_h6_ccu.h>
+
+#define PLL_PERI0_CTRL_REG 0x020
+#define AHB3_CFG_REG 0x51c
+#define APB2_CFG_REG 0x524
+#define MBUS_CFG_REG 0x540
+#define DE_BGR_REG 0x60c
+#define DI_BGR_REG 0x62c
+#define GPU_BGR_REG 0x67c
+#define CE_BGR_REG 0x68c
+#define VE_BGR_REG 0x69c
+#define EMCE_BGR_REG 0x6bc
+#define VP9_BGR_REG 0x6cc
+#define DMA_BGR_REG 0x70c
+#define MSGBOX_BGR_REG 0x71c
+#define SPINLOCK_BGR_REG 0x72c
+#define HSTIMER_BGR_REG 0x73c
+#define DBGSYS_BGR_REG 0x78c
+#define PSI_BGR_REG 0x79c
+#define PWM_BGR_REG 0x7ac
+#define DRAM_CLK_REG 0x800
+#define NAND_BGR_REG 0x82c
+#define SMHC0_CLK_REG 0x830
+#define SMHC1_CLK_REG 0x834
+#define SMHC2_CLK_REG 0x838
+#define SMHC_BGR_REG 0x84c
+#define UART_BGR_REG 0x90c
+#define TWI_BGR_REG 0x91c
+#define SCR_BGR_REG 0x93c
+#define SPI_BGR_REG 0x96c
+#define EMAC_BGR_REG 0x97c
+#define TS_BGR_REG 0x9bc
+#define CIRTX_BGR_REG 0x9cc
+#define THS_BGR_REG 0x9fc
+#define I2S_PCM_BGR_REG 0xa1c
+#define OWA_BGR_REG 0xa2c
+#define DMIC_BGR_REG 0xa4c
+#define AUDIO_HUB_BGR_REG 0xa6c
+#define USB0_CLK_REG 0xa70
+#define USB1_CLK_REG 0xa74
+#define USB3_CLK_REG 0xa7c
+#define USB_BGR_REG 0xa8c
+#define PCIE_BGR_REG 0xabc
+#define HDMI_BGR_REG 0xb1c
+#define DISPLAY_IF_TOP_BGR_REG 0xb5c
+#define TCON_LCD_BGR_REG 0xb7c
+#define TCON_TV_BGR_REG 0xb9c
+#define CSI_BGR_REG 0xc2c
+#define HDMI_HDCP_BGR_REG 0xc4c
+
+static int sun50i_h6_ccu_match(device_t, cfdata_t, void *);
+static void sun50i_h6_ccu_attach(device_t, device_t, void *);
+
+static const char * const compatible[] = {
+ "allwinner,sun50i-h6-ccu",
+ NULL
+};
+
+CFATTACH_DECL_NEW(sunxi_h6_ccu, sizeof(struct sunxi_ccu_softc),
+ sun50i_h6_ccu_match, sun50i_h6_ccu_attach, NULL, NULL);
+
+static struct sunxi_ccu_reset sun50i_h6_ccu_resets[] = {
+ SUNXI_CCU_RESET(H6_RST_MBUS, MBUS_CFG_REG, 30),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_DE, DE_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_DEINTERLACE, DI_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_GPU, GPU_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_CE, CE_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_VE, VE_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_EMCE, EMCE_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_VP9, VP9_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_DMA, DMA_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_MSGBOX, MSGBOX_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_SPINLOCK, SPINLOCK_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_HSTIMER, HSTIMER_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_DBG, DBGSYS_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_PSI, PSI_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_PWM, PWM_BGR_REG, 16),
+
+ /* H6_RST_BUS_IOMMU: No bit defined in user manual */
+
+ SUNXI_CCU_RESET(H6_RST_BUS_DRAM, DRAM_CLK_REG, 30),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_NAND, NAND_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_MMC0, SMHC_BGR_REG, 16),
+ SUNXI_CCU_RESET(H6_RST_BUS_MMC1, SMHC_BGR_REG, 17),
+ SUNXI_CCU_RESET(H6_RST_BUS_MMC2, SMHC_BGR_REG, 18),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_UART0, UART_BGR_REG, 16),
+ SUNXI_CCU_RESET(H6_RST_BUS_UART1, UART_BGR_REG, 17),
+ SUNXI_CCU_RESET(H6_RST_BUS_UART2, UART_BGR_REG, 18),
+ SUNXI_CCU_RESET(H6_RST_BUS_UART3, UART_BGR_REG, 19),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_I2C0, TWI_BGR_REG, 16),
+ SUNXI_CCU_RESET(H6_RST_BUS_I2C1, TWI_BGR_REG, 17),
+ SUNXI_CCU_RESET(H6_RST_BUS_I2C2, TWI_BGR_REG, 18),
+ SUNXI_CCU_RESET(H6_RST_BUS_I2C3, TWI_BGR_REG, 19),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_SCR0, SCR_BGR_REG, 16),
+ SUNXI_CCU_RESET(H6_RST_BUS_SCR1, SCR_BGR_REG, 17),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_SPI0, SPI_BGR_REG, 16),
+ SUNXI_CCU_RESET(H6_RST_BUS_SPI1, SPI_BGR_REG, 17),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_EMAC, EMAC_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_TS, TS_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_IR_TX, CIRTX_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_THS, THS_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_I2S0, I2S_PCM_BGR_REG, 16),
+ SUNXI_CCU_RESET(H6_RST_BUS_I2S1, I2S_PCM_BGR_REG, 17),
+ SUNXI_CCU_RESET(H6_RST_BUS_I2S2, I2S_PCM_BGR_REG, 18),
+ SUNXI_CCU_RESET(H6_RST_BUS_I2S3, I2S_PCM_BGR_REG, 19),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_SPDIF, OWA_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_DMIC, DMIC_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_AUDIO_HUB, AUDIO_HUB_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_USB_PHY0, USB0_CLK_REG, 30),
+
+ SUNXI_CCU_RESET(H6_RST_USB_PHY1, USB1_CLK_REG, 30),
+
+ SUNXI_CCU_RESET(H6_RST_USB_PHY3, USB3_CLK_REG, 30),
+ SUNXI_CCU_RESET(H6_RST_USB_HSIC, USB3_CLK_REG, 28),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_OHCI0, USB_BGR_REG, 16),
+ SUNXI_CCU_RESET(H6_RST_BUS_OHCI3, USB_BGR_REG, 19),
+ SUNXI_CCU_RESET(H6_RST_BUS_EHCI0, USB_BGR_REG, 20),
+ SUNXI_CCU_RESET(H6_RST_BUS_XHCI, USB_BGR_REG, 21),
+ SUNXI_CCU_RESET(H6_RST_BUS_EHCI3, USB_BGR_REG, 23),
+ SUNXI_CCU_RESET(H6_RST_BUS_OTG, USB_BGR_REG, 24),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_PCIE, PCIE_BGR_REG, 16),
+ SUNXI_CCU_RESET(H6_RST_PCIE_POWERUP, PCIE_BGR_REG, 17),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_HDMI, HDMI_BGR_REG, 16),
+ SUNXI_CCU_RESET(H6_RST_BUS_HDMI_SUB, HDMI_BGR_REG, 17),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_TCON_TOP, DISPLAY_IF_TOP_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_TCON_LCD0, TCON_LCD_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_TCON_TV0, TCON_TV_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_CSI, CSI_BGR_REG, 16),
+
+ SUNXI_CCU_RESET(H6_RST_BUS_HDCP, HDMI_HDCP_BGR_REG, 16),
+};
+
+static const char *ahb3_parents[] = { "hosc", "losc", "psi", "pll_periph0" };
+static const char *apb2_parents[] = { "hosc", "losc", "psi", "pll_periph0" };
+static const char *mod_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" };
+
+static struct sunxi_ccu_clk sun50i_h6_ccu_clks[] = {
+ SUNXI_CCU_FIXED_FACTOR(H6_CLK_OSC12M, "osc12m", "hosc", 2, 1),
+
+ SUNXI_CCU_NKMP(H6_CLK_PLL_PERIPH0_4X, "pll_periph0_4x", "hosc",
+ PLL_PERI0_CTRL_REG, /* reg */
+ __BITS(15,8), /* n */
+ 0, /* k */
+ __BIT(1), /* m */
+ __BIT(0), /* p */
+ __BIT(31), /* enable */
+ 0),
+ SUNXI_CCU_FIXED_FACTOR(H6_CLK_PLL_PERIPH0_2X, "pll_periph0_2x", "pll_periph0_4x", 2, 1),
+ SUNXI_CCU_FIXED_FACTOR(H6_CLK_PLL_PERIPH0, "pll_periph0", "pll_periph0_4x", 4, 1),
+
+ SUNXI_CCU_NM(H6_CLK_AHB3, "ahb3", ahb3_parents,
+ AHB3_CFG_REG, /* reg */
+ __BITS(9,8), /* n */
+ __BITS(1,0), /* m */
+ __BITS(25,24), /* sel */
+ 0, /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO),
+
+ SUNXI_CCU_NM(H6_CLK_APB2, "apb2", apb2_parents,
+ APB2_CFG_REG, /* reg */
+ __BITS(9,8), /* n */
+ __BITS(1,0), /* m */
+ __BITS(25,24), /* sel */
+ 0, /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO),
+
+ SUNXI_CCU_NM(H6_CLK_MMC0, "mmc0", mod_parents,
+ SMHC0_CLK_REG, /* reg */
+ __BITS(9,8), /* n */
+ __BITS(3,0), /* m */
+ __BITS(25,24), /* sel */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+ SUNXI_CCU_NM(H6_CLK_MMC1, "mmc1", mod_parents,
+ SMHC1_CLK_REG, /* reg */
+ __BITS(9,8), /* n */
+ __BITS(3,0), /* m */
+ __BITS(25,24), /* sel */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+ SUNXI_CCU_NM(H6_CLK_MMC2, "mmc2", mod_parents,
+ SMHC2_CLK_REG, /* reg */
+ __BITS(9,8), /* n */
+ __BITS(3,0), /* m */
+ __BITS(25,24), /* sel */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+ SUNXI_CCU_GATE(H6_CLK_BUS_MMC0, "bus-mmc0", "mmc0",
+ SMHC_BGR_REG, 0),
+ SUNXI_CCU_GATE(H6_CLK_BUS_MMC1, "bus-mmc1", "mmc1",
+ SMHC_BGR_REG, 1),
+ SUNXI_CCU_GATE(H6_CLK_BUS_MMC2, "bus-mmc2", "mmc2",
+ SMHC_BGR_REG, 2),
+
+ SUNXI_CCU_GATE(H6_CLK_BUS_UART0, "bus-uart0", "apb2",
+ UART_BGR_REG, 0),
+ SUNXI_CCU_GATE(H6_CLK_BUS_UART1, "bus-uart1", "apb2",
+ UART_BGR_REG, 1),
+ SUNXI_CCU_GATE(H6_CLK_BUS_UART2, "bus-uart2", "apb2",
+ UART_BGR_REG, 2),
+ SUNXI_CCU_GATE(H6_CLK_BUS_UART3, "bus-uart3", "apb2",
+ UART_BGR_REG, 3),
+
+ SUNXI_CCU_GATE(H6_CLK_BUS_I2C0, "bus-i2c0", "apb2",
+ TWI_BGR_REG, 0),
+ SUNXI_CCU_GATE(H6_CLK_BUS_I2C1, "bus-i2c1", "apb2",
+ TWI_BGR_REG, 1),
+ SUNXI_CCU_GATE(H6_CLK_BUS_I2C2, "bus-i2c2", "apb2",
+ TWI_BGR_REG, 2),
+ SUNXI_CCU_GATE(H6_CLK_BUS_I2C3, "bus-i2c3", "apb2",
+ TWI_BGR_REG, 3),
+
+ SUNXI_CCU_GATE(H6_CLK_USB_OHCI0, "usb-ohci0", "ahb3",
+ USB0_CLK_REG, 31),
+ SUNXI_CCU_GATE(H6_CLK_USB_PHY0, "usb-phy0", "ahb3",
+ USB0_CLK_REG, 29),
+
+ SUNXI_CCU_GATE(H6_CLK_USB_PHY1, "usb-phy1", "ahb3",
+ USB1_CLK_REG, 29),
+
+ SUNXI_CCU_GATE(H6_CLK_USB_OHCI3, "usb-ohci3", "ahb3",
+ USB3_CLK_REG, 31),
+ SUNXI_CCU_GATE(H6_CLK_USB_PHY3, "usb-phy3", "ahb3",
+ USB3_CLK_REG, 29),
+ SUNXI_CCU_GATE(H6_CLK_USB_HSIC_12M, "usb-hsic-12m", "osc12m",
+ USB3_CLK_REG, 27),
+ SUNXI_CCU_GATE(H6_CLK_USB_HSIC, "usb-hsic", "ahb3",
+ USB3_CLK_REG, 26),
+
+ SUNXI_CCU_GATE(H6_CLK_BUS_OHCI0, "bus-ohci0", "ahb3",
+ USB_BGR_REG, 0),
+ SUNXI_CCU_GATE(H6_CLK_BUS_OHCI3, "bus-ohci3", "ahb3",
+ USB_BGR_REG, 3),
+ SUNXI_CCU_GATE(H6_CLK_BUS_EHCI0, "bus-ehci0", "ahb3",
+ USB_BGR_REG, 4),
+ SUNXI_CCU_GATE(H6_CLK_BUS_XHCI, "bus-xhci", "ahb3",
+ USB_BGR_REG, 5),
+ SUNXI_CCU_GATE(H6_CLK_BUS_EHCI3, "bus-ehci3", "ahb3",
+ USB_BGR_REG, 7),
+ SUNXI_CCU_GATE(H6_CLK_BUS_OTG, "bus-otg", "ahb3",
+ USB_BGR_REG, 8),
+
+ SUNXI_CCU_GATE(H6_CLK_BUS_EMAC, "bus-emac", "ahb3",
+ EMAC_BGR_REG, 0),
+};
+
+static int
+sun50i_h6_ccu_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+sun50i_h6_ccu_attach(device_t parent, device_t self, void *aux)
+{
+ struct sunxi_ccu_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+
+ sc->sc_dev = self;
+ sc->sc_phandle = faa->faa_phandle;
+ sc->sc_bst = faa->faa_bst;
+
+ sc->sc_resets = sun50i_h6_ccu_resets;
+ sc->sc_nresets = __arraycount(sun50i_h6_ccu_resets);
+
+ sc->sc_clks = sun50i_h6_ccu_clks;
+ sc->sc_nclks = __arraycount(sun50i_h6_ccu_clks);
+
+ if (sunxi_ccu_attach(sc) != 0)
+ return;
+
+ aprint_naive("\n");
+ aprint_normal(": H6 CCU\n");
+
+ sunxi_ccu_print(sc);
+}
Index: src/sys/arch/arm/sunxi/sun50i_h6_ccu.h
diff -u /dev/null src/sys/arch/arm/sunxi/sun50i_h6_ccu.h:1.1
--- /dev/null Tue May 1 19:53:14 2018
+++ src/sys/arch/arm/sunxi/sun50i_h6_ccu.h Tue May 1 19:53:14 2018
@@ -0,0 +1,235 @@
+/* $NetBSD: sun50i_h6_ccu.h,v 1.1 2018/05/01 19:53:14 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2018 Jared McNeill <jmcne...@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _SUN50I_H6_CCU_H
+#define _SUN50I_H6_CCU_H
+
+#define H6_RST_MBUS 0
+#define H6_RST_BUS_DE 1
+#define H6_RST_BUS_DEINTERLACE 2
+#define H6_RST_BUS_GPU 3
+#define H6_RST_BUS_CE 4
+#define H6_RST_BUS_VE 5
+#define H6_RST_BUS_EMCE 6
+#define H6_RST_BUS_VP9 7
+#define H6_RST_BUS_DMA 8
+#define H6_RST_BUS_MSGBOX 9
+#define H6_RST_BUS_SPINLOCK 10
+#define H6_RST_BUS_HSTIMER 11
+#define H6_RST_BUS_DBG 12
+#define H6_RST_BUS_PSI 13
+#define H6_RST_BUS_PWM 14
+#define H6_RST_BUS_IOMMU 15
+#define H6_RST_BUS_DRAM 16
+#define H6_RST_BUS_NAND 17
+#define H6_RST_BUS_MMC0 18
+#define H6_RST_BUS_MMC1 19
+#define H6_RST_BUS_MMC2 20
+#define H6_RST_BUS_UART0 21
+#define H6_RST_BUS_UART1 22
+#define H6_RST_BUS_UART2 23
+#define H6_RST_BUS_UART3 24
+#define H6_RST_BUS_I2C0 25
+#define H6_RST_BUS_I2C1 26
+#define H6_RST_BUS_I2C2 27
+#define H6_RST_BUS_I2C3 28
+#define H6_RST_BUS_SCR0 29
+#define H6_RST_BUS_SCR1 30
+#define H6_RST_BUS_SPI0 31
+#define H6_RST_BUS_SPI1 32
+#define H6_RST_BUS_EMAC 33
+#define H6_RST_BUS_TS 34
+#define H6_RST_BUS_IR_TX 35
+#define H6_RST_BUS_THS 36
+#define H6_RST_BUS_I2S0 37
+#define H6_RST_BUS_I2S1 38
+#define H6_RST_BUS_I2S2 39
+#define H6_RST_BUS_I2S3 40
+#define H6_RST_BUS_SPDIF 41
+#define H6_RST_BUS_DMIC 42
+#define H6_RST_BUS_AUDIO_HUB 43
+#define H6_RST_USB_PHY0 44
+#define H6_RST_USB_PHY1 45
+#define H6_RST_USB_PHY3 46
+#define H6_RST_USB_HSIC 47
+#define H6_RST_BUS_OHCI0 48
+#define H6_RST_BUS_OHCI3 49
+#define H6_RST_BUS_EHCI0 50
+#define H6_RST_BUS_XHCI 51
+#define H6_RST_BUS_EHCI3 52
+#define H6_RST_BUS_OTG 53
+#define H6_RST_BUS_PCIE 54
+#define H6_RST_PCIE_POWERUP 55
+#define H6_RST_BUS_HDMI 56
+#define H6_RST_BUS_HDMI_SUB 57
+#define H6_RST_BUS_TCON_TOP 58
+#define H6_RST_BUS_TCON_LCD0 59
+#define H6_RST_BUS_TCON_TV0 60
+#define H6_RST_BUS_CSI 61
+#define H6_RST_BUS_HDCP 62
+
+#define H6_CLK_OSC12M 0
+#define H6_CLK_PLL_CPUX 1
+#define H6_CLK_PLL_DDR0 2
+#define H6_CLK_PLL_PERIPH0 3
+#define H6_CLK_PLL_PERIPH0_2X 4
+#define H6_CLK_PLL_PERIPH0_4X 5
+#define H6_CLK_PLL_PERIPH1 6
+#define H6_CLK_PLL_PERIPH1_2X 7
+#define H6_CLK_PLL_PERIPH1_4X 8
+#define H6_CLK_PLL_GPU 9
+#define H6_CLK_PLL_VIDEO0 10
+#define H6_CLK_PLL_VIDEO0_4X 11
+#define H6_CLK_PLL_VIDEO1 12
+#define H6_CLK_PLL_VIDEO1_4X 13
+#define H6_CLK_PLL_VE 14
+#define H6_CLK_PLL_DE 15
+#define H6_CLK_PLL_HSIC 16
+#define H6_CLK_PLL_AUDIO_BASE 17
+#define H6_CLK_PLL_AUDIO 18
+#define H6_CLK_PLL_AUDIO_2X 19
+#define H6_CLK_PLL_AUDIO_4X 20
+#define H6_CLK_CPUX 21
+#define H6_CLK_AXI 22
+#define H6_CLK_CPUX_APB 23
+#define H6_CLK_PSI_AHB1_AHB2 24
+#define H6_CLK_AHB3 25
+#define H6_CLK_APB1 26
+#define H6_CLK_APB2 27
+#define H6_CLK_MBUS 28
+#define H6_CLK_DE 29
+#define H6_CLK_BUS_DE 30
+#define H6_CLK_DEINTERLACE 31
+#define H6_CLK_BUS_DEINTERLACE 32
+#define H6_CLK_GPU 33
+#define H6_CLK_BUS_GPU 34
+#define H6_CLK_CE 35
+#define H6_CLK_BUS_CE 36
+#define H6_CLK_VE 37
+#define H6_CLK_BUS_VE 38
+#define H6_CLK_EMCE 39
+#define H6_CLK_BUS_EMCE 40
+#define H6_CLK_VP9 41
+#define H6_CLK_BUS_VP9 42
+#define H6_CLK_BUS_DMA 43
+#define H6_CLK_BUS_MSGBOX 44
+#define H6_CLK_BUS_SPINLOCK 45
+#define H6_CLK_BUS_HSTIMER 46
+#define H6_CLK_AVS 47
+#define H6_CLK_BUS_DBG 48
+#define H6_CLK_BUS_PSI 49
+#define H6_CLK_BUS_PWM 50
+#define H6_CLK_BUS_IOMMU 51
+#define H6_CLK_DRAM 52
+#define H6_CLK_MBUS_DMA 53
+#define H6_CLK_MBUS_VE 54
+#define H6_CLK_MBUS_CE 55
+#define H6_CLK_MBUS_TS 56
+#define H6_CLK_MBUS_NAND 57
+#define H6_CLK_MBUS_CSI 58
+#define H6_CLK_MBUS_DEINTERLACE 59
+#define H6_CLK_BUS_DRAM 60
+#define H6_CLK_NAND0 61
+#define H6_CLK_NAND1 62
+#define H6_CLK_BUS_NAND 63
+#define H6_CLK_MMC0 64
+#define H6_CLK_MMC1 65
+#define H6_CLK_MMC2 66
+#define H6_CLK_BUS_MMC0 67
+#define H6_CLK_BUS_MMC1 68
+#define H6_CLK_BUS_MMC2 69
+#define H6_CLK_BUS_UART0 70
+#define H6_CLK_BUS_UART1 71
+#define H6_CLK_BUS_UART2 72
+#define H6_CLK_BUS_UART3 73
+#define H6_CLK_BUS_I2C0 74
+#define H6_CLK_BUS_I2C1 75
+#define H6_CLK_BUS_I2C2 76
+#define H6_CLK_BUS_I2C3 77
+#define H6_CLK_BUS_SCR0 78
+#define H6_CLK_BUS_SCR1 79
+#define H6_CLK_SPI0 80
+#define H6_CLK_SPI1 81
+#define H6_CLK_BUS_SPI0 82
+#define H6_CLK_BUS_SPI1 83
+#define H6_CLK_BUS_EMAC 84
+#define H6_CLK_TS 85
+#define H6_CLK_BUS_TS 86
+#define H6_CLK_IR_TX 87
+#define H6_CLK_BUS_IR_TX 88
+#define H6_CLK_BUS_THS 89
+#define H6_CLK_I2S3 90
+#define H6_CLK_I2S0 91
+#define H6_CLK_I2S1 92
+#define H6_CLK_I2S2 93
+#define H6_CLK_BUS_I2S0 94
+#define H6_CLK_BUS_I2S1 95
+#define H6_CLK_BUS_I2S2 96
+#define H6_CLK_BUS_I2S3 97
+#define H6_CLK_SPDIF 98
+#define H6_CLK_BUS_SPDIF 99
+#define H6_CLK_DMIC 100
+#define H6_CLK_BUS_DMIC 101
+#define H6_CLK_AUDIO_HUB 102
+#define H6_CLK_BUS_AUDIO_HUB 103
+#define H6_CLK_USB_OHCI0 104
+#define H6_CLK_USB_PHY0 105
+#define H6_CLK_USB_PHY1 106
+#define H6_CLK_USB_OHCI3 107
+#define H6_CLK_USB_PHY3 108
+#define H6_CLK_USB_HSIC_12M 109
+#define H6_CLK_USB_HSIC 110
+#define H6_CLK_BUS_OHCI0 111
+#define H6_CLK_BUS_OHCI3 112
+#define H6_CLK_BUS_EHCI0 113
+#define H6_CLK_BUS_XHCI 114
+#define H6_CLK_BUS_EHCI3 115
+#define H6_CLK_BUS_OTG 116
+#define H6_CLK_PCIE_REF_100M 117
+#define H6_CLK_PCIE_REF 118
+#define H6_CLK_PCIE_REF_OUT 119
+#define H6_CLK_PCIE_MAXI 120
+#define H6_CLK_PCIE_AUX 121
+#define H6_CLK_BUS_PCIE 122
+#define H6_CLK_HDMI 123
+#define H6_CLK_HDMI_SLOW 124
+#define H6_CLK_HDMI_CEC 125
+#define H6_CLK_BUS_HDMI 126
+#define H6_CLK_BUS_TCON_TOP 127
+#define H6_CLK_TCON_LCD0 128
+#define H6_CLK_BUS_TCON_LCD0 129
+#define H6_CLK_TCON_TV0 130
+#define H6_CLK_BUS_TCON_TV0 131
+#define H6_CLK_CSI_CCI 132
+#define H6_CLK_CSI_TOP 133
+#define H6_CLK_CSI_MCLK 134
+#define H6_CLK_BUS_CSI 135
+#define H6_CLK_HDCP 136
+#define H6_CLK_BUS_HDCP 137
+
+#endif /* !_SUN50I_H6_CCU_H */
