CVSROOT: /cvs
Module name: src
Changes by: [email protected] 2009/08/06 15:11:39
Modified files:
sys/arch/mips64/conf: files.mips64
sys/arch/mips64/include: archtype.h cpu.h
sys/arch/mips64/mips64: context.S cpu.c tlbhandler.S
Added files:
sys/arch/mips64/include: loongson2.h
sys/arch/mips64/mips64: cache_loongson2.S
Log message:
Work in progress support for Loongson2E/2F processors; need option CPU_LOONGSON2
in the kernel to be brought in, due to invasive differences in tlb operation.
Comes with a separate cache operations file due to the cache being R5k-style
with R10k-style way number encoding.
