All the websites say it's supported for the T5220, but I don't seem to be able
to get it to netboot....
...
2017-04-19 19:37:32.850 0:0:0>
2017-04-19 19:37:32.899 0:0:0>POST 4.33.6.d 2013/07/23 10:30
2017-04-19 19:37:32.997 0:0:0>
2017-04-19 19:37:33.061 0:0:0>Copyright (c) 2013, Oracle and/or its affiliates.
All rights reserved.
2017-04-19 19:37:33.264 0:0:0>vbsc_input_location 000000ff.f0e04c00
2017-04-19 19:37:33.371 0:0:0>POST enabling CMP 0 threads: ffffffff.ffffffff
2017-04-19 19:37:33.498 0:0:0>VBSC mode is: 00000000.00000001
2017-04-19 19:37:33.596 0:0:0>VBSC level is: 00000000.00000001
2017-04-19 19:37:33.696 0:0:0>VBSC selecting Normal mode, MAX Testing.
2017-04-19 19:37:33.810 0:0:0>VBSC setting verbosity level 3
2017-04-19 19:37:33.906 0:0:0> Niagara2, Version 2.1
2017-04-19 19:37:34.001 0:0:0> Serial Number: 3fb4006d.abe11903
2017-04-19 19:37:35.102 0:0:0> CMP 1166 Mhz
2017-04-19 19:37:35.176 0:0:0>Basic Memory Tests.....
2017-04-19 19:37:35.273 0:0:0>Begin: Branch Sanity Check
2017-04-19 19:37:35.373 0:0:0>End : Branch Sanity Check
2017-04-19 19:37:36.512 0:0:0>Sys 166 MHz, CPU 1166 MHz, Mem 332 MHz
2017-04-19 19:37:36.622 0:0:0>CMP 1166 MHz
2017-04-19 19:37:36.691 0:0:0>L2 Bank EFuse = 00000000.000000ff
2017-04-19 19:37:36.793 0:0:0>L2 Bank status = 00000000.00000f0f
2017-04-19 19:37:36.901 0:0:0>Core available Efuse = ffffffff.ffffffff
2017-04-19 19:37:37.017 0:0:0>Test Memory.....
2017-04-19 19:37:37.102 0:0:0>Begin: Probe and Setup Memory
2017-04-19 19:37:37.203 0:0:0>INFO: 8192MB at Memory Branch 0
2017-04-19 19:37:37.305 0:0:0>INFO: 8192MB at Memory Branch 1
2017-04-19 19:37:37.407 0:0:0>INFO: 8192MB at Memory Branch 2
2017-04-19 19:37:37.509 0:0:0>INFO: 8192MB at Memory Branch 3
2017-04-19 19:37:37.615 0:0:0>
2017-04-19 19:37:37.675 0:0:0>End : Probe and Setup Memory
2017-04-19 19:37:37.776 0:0:0>Setup POST Mailbox .....
2017-04-19 19:37:37.874 0:0:0>Begin: Test Mailbox region
2017-04-19 19:37:37.965 0:0:0>..
2017-04-19 19:37:52.845 0:0:0>End : Test Mailbox region
2017-04-19 19:37:52.945 0:0:0>Begin: Set Mailbox
2017-04-19 19:37:56.433 0:0:0>Master CPU Tests Basic.....
2017-04-19 19:37:56.697 0:0:0>CPU =: 0
2017-04-19 19:37:57.063 0:0:0>Begin: DMMU Registers Access
2017-04-19 19:37:57.474 0:0:0>End : DMMU Registers Access
2017-04-19 19:37:57.640 0:0:0>Begin: IMMU Registers Access
2017-04-19 19:37:58.042 0:0:0>End : IMMU Registers Access
2017-04-19 19:37:58.207 0:0:0>Begin: Common MMU regs
2017-04-19 19:37:58.897 0:0:0>End : Common MMU regs
2017-04-19 19:37:59.262 0:0:0>Init MMU.....
2017-04-19 19:38:06.145 0:0:0>Sys 166 MHz, CPU 1166 MHz, Mem 332 MHz
2017-04-19 19:38:06.317 0:0:0>CMP 1166 MHz
2017-04-19 19:38:06.457 0:0:0>Begin: Setup Final DMMU Entries
2017-04-19 19:38:06.813 0:0:0>End : Setup Final DMMU Entries
2017-04-19 19:38:06.996 0:0:0>Copy POST to memory..
2017-04-19 19:38:17.988 0:0:0>Verifying checksum on copied image.
2017-04-19 19:38:18.151 0:0:0>The Memory's CHECKSUM value is 8a3f.
2017-04-19 19:38:18.316 0:0:0>The Memory's Content Size value is b82ba.
2017-04-19 19:38:30.500 0:0:0>Success... Checksum on Memory Validated.
2017-04-19 19:38:30.667 0:0:0>Executing out of memory..
2017-04-19 19:38:30.723 0:0:0>NCU Setup and PIU link train.....
2017-04-19 19:38:30.780 0:0:0>Begin: NCU INIT PCIE Base and Mask Regs.
2017-04-19 19:38:31.002 0:0:0>End : NCU INIT PCIE Base and Mask Regs.
2017-04-19 19:38:31.058 0:0:0>Begin: PIU link train
2017-04-19 19:38:32.564 0:0:0>End : PIU link train
2017-04-19 19:38:32.619 0:0:0>L2 Tests.....
2017-04-19 19:38:32.674 0:0:0>Begin: Setup L2 Cache
2017-04-19 19:38:32.688 0:0:0>End : Setup L2 Cache
2017-04-19 19:38:32.746 0:0:0>Begin: L2 Cache UA Array Test
2017-04-19 19:38:32.868 0:0:0>End : L2 Cache UA Array Test
2017-04-19 19:38:32.924 0:0:0>Begin: L2 Cache VD Array Test
2017-04-19 19:38:33.044 0:0:0>End : L2 Cache VD Array Test
2017-04-19 19:38:33.100 0:0:0>Begin: L2 Cache Tags Test
2017-04-19 19:38:33.320 0:0:0>End : L2 Cache Tags Test
2017-04-19 19:38:33.376 0:0:0>Begin: Scrub and Setup L2 Cache
2017-04-19 19:38:33.484 0:0:0>L2 Scrub VD & UA
2017-04-19 19:38:33.541 0:0:0>L2 Scrub Tags
2017-04-19 19:38:33.689 0:0:0>End : Scrub and Setup L2 Cache
2017-04-19 19:38:33.746 0:0:0>Begin: CMP Cache Ram Test
2017-04-19 19:38:36.717 0:0:0>End : CMP Cache Ram Test
2017-04-19 19:38:36.773 0:0:0>Begin: Enable CMP Cache
2017-04-19 19:38:36.880 0:0:0>Selected mode = 0
2017-04-19 19:38:36.934 0:0:0>L2 Scrub Data
2017-04-19 19:38:37.493 0:0:0>L2 Enable
2017-04-19 19:38:37.599 0:0:0>End : Enable CMP Cache
2017-04-19 19:38:39.244 0:0:0>CPU =: 0 8 16 24 32 40 48 56
2017-04-19 19:38:39.836 0:1:0>Begin: DMMU Registers Access
2017-04-19 19:38:39.841 0:2:0>Begin: DMMU Registers Access
2017-04-19 19:38:39.848 0:3:0>Begin: DMMU Registers Access
2017-04-19 19:38:39.853 0:4:0>Begin: DMMU Registers Access
2017-04-19 19:38:39.858 0:5:0>Begin: DMMU Registers Access
2017-04-19 19:38:39.864 0:6:0>Begin: DMMU Registers Access
2017-04-19 19:38:39.871 0:7:0>Begin: DMMU Registers Access
2017-04-19 19:38:39.897 0:1:0>End : DMMU Registers Access
2017-04-19 19:38:39.903 0:2:0>End : DMMU Registers Access
2017-04-19 19:38:39.908 0:3:0>End : DMMU Registers Access
2017-04-19 19:38:39.913 0:4:0>End : DMMU Registers Access
2017-04-19 19:38:39.919 0:5:0>End : DMMU Registers Access
2017-04-19 19:38:39.924 0:6:0>End : DMMU Registers Access
2017-04-19 19:38:39.930 0:7:0>End : DMMU Registers Access
2017-04-19 19:38:39.935 0:1:0>Begin: IMMU Registers Access
2017-04-19 19:38:39.940 0:2:0>Begin: IMMU Registers Access
2017-04-19 19:38:39.944 0:3:0>Begin: IMMU Registers Access
2017-04-19 19:38:39.949 0:4:0>Begin: IMMU Registers Access
2017-04-19 19:38:39.955 0:5:0>Begin: IMMU Registers Access
2017-04-19 19:38:39.960 0:6:0>Begin: IMMU Registers Access
2017-04-19 19:38:39.967 0:7:0>Begin: IMMU Registers Access
2017-04-19 19:38:39.990 0:1:0>End : IMMU Registers Access
2017-04-19 19:38:39.996 0:2:0>End : IMMU Registers Access
2017-04-19 19:38:40.002 0:3:0>End : IMMU Registers Access
2017-04-19 19:38:40.010 0:4:0>End : IMMU Registers Access
2017-04-19 19:38:40.015 0:5:0>End : IMMU Registers Access
2017-04-19 19:38:40.021 0:6:0>End : IMMU Registers Access
2017-04-19 19:38:40.028 0:7:0>End : IMMU Registers Access
2017-04-19 19:38:40.034 0:1:0>Begin: Common MMU regs
2017-04-19 19:38:40.042 0:2:0>Begin: Common MMU regs
2017-04-19 19:38:40.047 0:3:0>Begin: Common MMU regs
2017-04-19 19:38:40.052 0:4:0>Begin: Common MMU regs
2017-04-19 19:38:40.057 0:5:0>Begin: Common MMU regs
2017-04-19 19:38:40.062 0:6:0>Begin: Common MMU regs
2017-04-19 19:38:40.067 0:7:0>Begin: Common MMU regs
2017-04-19 19:38:40.091 0:1:0>End : Common MMU regs
2017-04-19 19:38:40.161 0:2:0>End : Common MMU regs
2017-04-19 19:38:40.167 0:3:0>End : Common MMU regs
2017-04-19 19:38:40.173 0:4:0>End : Common MMU regs
2017-04-19 19:38:40.184 0:5:0>End : Common MMU regs
2017-04-19 19:38:40.189 0:6:0>End : Common MMU regs
2017-04-19 19:38:40.195 0:7:0>End : Common MMU regs
2017-04-19 19:38:40.811 0:1:0>Begin: D-Cache RAM
2017-04-19 19:38:40.818 0:2:0>Begin: D-Cache RAM
2017-04-19 19:38:40.823 0:3:0>Begin: D-Cache RAM
2017-04-19 19:38:40.830 0:4:0>Begin: D-Cache RAM
2017-04-19 19:38:40.836 0:5:0>Begin: D-Cache RAM
2017-04-19 19:38:40.841 0:6:0>Begin: D-Cache RAM
2017-04-19 19:38:40.847 0:7:0>Begin: D-Cache RAM
2017-04-19 19:38:40.853 0:0:0>Extended CPU Tests.....
2017-04-19 19:38:40.881 0:1:0>End : D-Cache RAM
2017-04-19 19:38:40.887 0:2:0>End : D-Cache RAM
2017-04-19 19:38:40.898 0:3:0>End : D-Cache RAM
2017-04-19 19:38:40.902 0:4:0>End : D-Cache RAM
2017-04-19 19:38:40.907 0:5:0>End : D-Cache RAM
2017-04-19 19:38:40.912 0:6:0>End : D-Cache RAM
2017-04-19 19:38:40.917 0:7:0>End : D-Cache RAM
2017-04-19 19:38:40.924 0:1:0>Begin: D-Cache Tags
2017-04-19 19:38:40.929 0:2:0>Begin: D-Cache Tags
2017-04-19 19:38:40.934 0:3:0>Begin: D-Cache Tags
2017-04-19 19:38:40.940 0:4:0>Begin: D-Cache Tags
2017-04-19 19:38:40.944 0:5:0>Begin: D-Cache Tags
2017-04-19 19:38:40.951 0:6:0>Begin: D-Cache Tags
2017-04-19 19:38:40.958 0:7:0>Begin: D-Cache Tags
2017-04-19 19:38:40.973 0:0:0>Begin: D-Cache RAM
2017-04-19 19:38:40.990 0:1:0>End : D-Cache Tags
2017-04-19 19:38:40.995 0:2:0>End : D-Cache Tags
2017-04-19 19:38:41.001 0:3:0>End : D-Cache Tags
2017-04-19 19:38:41.007 0:4:0>End : D-Cache Tags
2017-04-19 19:38:41.013 0:5:0>End : D-Cache Tags
2017-04-19 19:38:41.027 0:6:0>End : D-Cache Tags
2017-04-19 19:38:41.032 0:7:0>End : D-Cache Tags
2017-04-19 19:38:41.038 0:1:0>Begin: I-Cache RAM Test
2017-04-19 19:38:41.043 0:2:0>Begin: I-Cache RAM Test
2017-04-19 19:38:41.048 0:3:0>Begin: I-Cache RAM Test
2017-04-19 19:38:41.053 0:4:0>Begin: I-Cache RAM Test
2017-04-19 19:38:41.059 0:5:0>Begin: I-Cache RAM Test
2017-04-19 19:38:41.064 0:6:0>Begin: I-Cache RAM Test
2017-04-19 19:38:41.069 0:7:0>Begin: I-Cache RAM Test
2017-04-19 19:38:41.074 0:0:0>End : D-Cache RAM
2017-04-19 19:38:41.088 0:0:0>Begin: D-Cache Tags
2017-04-19 19:38:41.112 0:1:0>End : I-Cache RAM Test
2017-04-19 19:38:41.118 0:2:0>End : I-Cache RAM Test
2017-04-19 19:38:41.124 0:3:0>End : I-Cache RAM Test
2017-04-19 19:38:41.129 0:4:0>End : I-Cache RAM Test
2017-04-19 19:38:41.134 0:5:0>End : I-Cache RAM Test
2017-04-19 19:38:41.141 0:6:0>End : I-Cache RAM Test
2017-04-19 19:38:41.146 0:7:0>End : I-Cache RAM Test
2017-04-19 19:38:41.153 0:1:0>Begin: I-Cache Tag RAM
2017-04-19 19:38:41.163 0:2:0>Begin: I-Cache Tag RAM
2017-04-19 19:38:41.169 0:3:0>Begin: I-Cache Tag RAM
2017-04-19 19:38:41.174 0:4:0>Begin: I-Cache Tag RAM
2017-04-19 19:38:41.179 0:5:0>Begin: I-Cache Tag RAM
2017-04-19 19:38:41.183 0:6:0>Begin: I-Cache Tag RAM
2017-04-19 19:38:41.188 0:7:0>Begin: I-Cache Tag RAM
2017-04-19 19:38:41.193 0:0:0>End : D-Cache Tags
2017-04-19 19:38:41.208 0:0:0>Begin: I-Cache RAM Test
2017-04-19 19:38:41.224 0:1:0>End : I-Cache Tag RAM
2017-04-19 19:38:41.229 0:2:0>End : I-Cache Tag RAM
2017-04-19 19:38:41.234 0:3:0>End : I-Cache Tag RAM
2017-04-19 19:38:41.239 0:4:0>End : I-Cache Tag RAM
2017-04-19 19:38:41.244 0:5:0>End : I-Cache Tag RAM
2017-04-19 19:38:41.258 0:6:0>End : I-Cache Tag RAM
2017-04-19 19:38:41.262 0:7:0>End : I-Cache Tag RAM
2017-04-19 19:38:41.277 0:0:0>End : I-Cache RAM Test
2017-04-19 19:38:41.293 0:0:0>Begin: I-Cache Tag RAM
2017-04-19 19:38:41.392 0:0:0>End : I-Cache Tag RAM
2017-04-19 19:38:54.272 0:0:0>CPU =: 0-63
2017-04-19 19:38:54.427 0:0:0>Test slave strand registers...
2017-04-19 19:39:04.199 0:0:0>Scrub Memory.....
2017-04-19 19:39:04.254 0:0:0>Begin: Scrub Memory
2017-04-19 19:39:04.401 0:0:0>Scrub 00000000.10000000->00000008.00000000
2017-04-19 19:39:08.807 0:0:0>End : Scrub Memory
2017-04-19 19:39:09.149 0:0:0>SPU CWQ Tests...
2017-04-19 19:39:09.643 0:0:0>MAU Tests...
2017-04-19 19:39:10.315 0:1:0>Begin: FPU Registers and Data Path
2017-04-19 19:39:10.396 0:2:0>Begin: FPU Registers and Data Path
2017-04-19 19:39:10.465 0:3:0>Begin: FPU Registers and Data Path
2017-04-19 19:39:10.545 0:4:0>Begin: FPU Registers and Data Path
2017-04-19 19:39:10.619 0:5:0>Begin: FPU Registers and Data Path
2017-04-19 19:39:10.696 0:6:0>Begin: FPU Registers and Data Path
2017-04-19 19:39:10.774 0:7:0>Begin: FPU Registers and Data Path
2017-04-19 19:39:11.279 0:0:0>Begin: FPU Registers and Data Path
2017-04-19 19:39:11.769 0:1:0>End : FPU Registers and Data Path
2017-04-19 19:39:11.849 0:2:0>End : FPU Registers and Data Path
2017-04-19 19:39:11.930 0:3:0>End : FPU Registers and Data Path
2017-04-19 19:39:12.010 0:4:0>End : FPU Registers and Data Path
2017-04-19 19:39:12.092 0:5:0>End : FPU Registers and Data Path
2017-04-19 19:39:12.171 0:6:0>End : FPU Registers and Data Path
2017-04-19 19:39:12.253 0:7:0>End : FPU Registers and Data Path
2017-04-19 19:39:12.386 0:1:0>Begin: FPU Move Registers
2017-04-19 19:39:12.462 0:2:0>Begin: FPU Move Registers
2017-04-19 19:39:12.534 0:3:0>Begin: FPU Move Registers
2017-04-19 19:39:12.606 0:4:0>Begin: FPU Move Registers
2017-04-19 19:39:12.679 0:5:0>Begin: FPU Move Registers
2017-04-19 19:39:12.752 0:6:0>Begin: FPU Move Registers
2017-04-19 19:39:12.826 0:7:0>Begin: FPU Move Registers
2017-04-19 19:39:12.902 0:0:0>End : FPU Registers and Data Path
2017-04-19 19:39:13.373 0:0:0>Begin: FPU Move Registers
2017-04-19 19:39:16.186 0:1:0>End : FPU Move Registers
2017-04-19 19:39:16.407 0:2:0>End : FPU Move Registers
2017-04-19 19:39:16.499 0:3:0>End : FPU Move Registers
2017-04-19 19:39:16.575 0:4:0>End : FPU Move Registers
2017-04-19 19:39:16.663 0:5:0>End : FPU Move Registers
2017-04-19 19:39:16.735 0:6:0>End : FPU Move Registers
2017-04-19 19:39:16.812 0:7:0>End : FPU Move Registers
2017-04-19 19:39:16.990 0:1:0>Begin: FSR Read/Write
2017-04-19 19:39:17.398 0:2:0>Begin: FSR Read/Write
2017-04-19 19:39:17.952 0:3:0>Begin: FSR Read/Write
2017-04-19 19:39:18.632 0:4:0>Begin: FSR Read/Write
2017-04-19 19:39:19.420 0:5:0>Begin: FSR Read/Write
2017-04-19 19:39:20.317 0:6:0>Begin: FSR Read/Write
2017-04-19 19:39:21.290 0:7:0>Begin: FSR Read/Write
2017-04-19 19:39:22.336 0:0:0>End : FPU Move Registers
2017-04-19 19:39:23.571 0:0:0>Begin: FSR Read/Write
2017-04-19 19:39:26.907 0:1:0>End : FSR Read/Write
2017-04-19 19:39:27.001 0:2:0>End : FSR Read/Write
2017-04-19 19:39:27.083 0:3:0>End : FSR Read/Write
2017-04-19 19:39:27.160 0:4:0>End : FSR Read/Write
2017-04-19 19:39:27.234 0:5:0>End : FSR Read/Write
2017-04-19 19:39:27.402 0:6:0>End : FSR Read/Write
2017-04-19 19:39:27.483 0:7:0>End : FSR Read/Write
2017-04-19 19:39:27.516 0:1:0>Begin: FPU Branch Instructions
2017-04-19 19:39:27.521 0:2:0>Begin: FPU Branch Instructions
2017-04-19 19:39:27.528 0:3:0>Begin: FPU Branch Instructions
2017-04-19 19:39:27.533 0:4:0>Begin: FPU Branch Instructions
2017-04-19 19:39:27.539 0:5:0>Begin: FPU Branch Instructions
2017-04-19 19:39:27.544 0:6:0>Begin: FPU Branch Instructions
2017-04-19 19:39:27.555 0:7:0>Begin: FPU Branch Instructions
2017-04-19 19:39:27.561 0:0:0>End : FSR Read/Write
2017-04-19 19:39:27.585 0:0:0>Begin: FPU Branch Instructions
2017-04-19 19:39:27.784 0:0:0>End : FPU Branch Instructions
2017-04-19 19:39:27.790 0:1:0>End : FPU Branch Instructions
2017-04-19 19:39:27.796 0:2:0>End : FPU Branch Instructions
2017-04-19 19:39:27.801 0:3:0>End : FPU Branch Instructions
2017-04-19 19:39:27.807 0:4:0>End : FPU Branch Instructions
2017-04-19 19:39:27.812 0:5:0>End : FPU Branch Instructions
2017-04-19 19:39:27.818 0:6:0>End : FPU Branch Instructions
2017-04-19 19:39:27.823 0:7:0>End : FPU Branch Instructions
2017-04-19 19:39:27.835 0:0:0>Begin: FPU Functional Test
2017-04-19 19:39:27.841 0:1:0>Begin: FPU Functional Test
2017-04-19 19:39:27.848 0:2:0>Begin: FPU Functional Test
2017-04-19 19:39:27.853 0:3:0>Begin: FPU Functional Test
2017-04-19 19:39:27.859 0:4:0>Begin: FPU Functional Test
2017-04-19 19:39:27.865 0:5:0>Begin: FPU Functional Test
2017-04-19 19:39:27.871 0:6:0>Begin: FPU Functional Test
2017-04-19 19:39:27.878 0:7:0>Begin: FPU Functional Test
2017-04-19 19:39:29.141 0:0:0>End : FPU Functional Test
2017-04-19 19:39:29.147 0:1:0>End : FPU Functional Test
2017-04-19 19:39:29.152 0:2:0>End : FPU Functional Test
2017-04-19 19:39:29.158 0:3:0>End : FPU Functional Test
2017-04-19 19:39:29.163 0:4:0>End : FPU Functional Test
2017-04-19 19:39:29.169 0:5:0>End : FPU Functional Test
2017-04-19 19:39:29.174 0:6:0>End : FPU Functional Test
2017-04-19 19:39:29.179 0:7:0>End : FPU Functional Test
2017-04-19 19:39:29.241 0:0:0>Begin: PIU INT init test
2017-04-19 19:39:29.455 0:0:0>End : PIU INT init test
2017-04-19 19:39:29.509 0:0:0>Begin: PIU MSI init test
2017-04-19 19:39:29.728 0:0:0>End : PIU MSI init test
2017-04-19 19:39:29.783 0:0:0>Begin: PIU ILU init test
2017-04-19 19:39:29.998 0:0:0>End : PIU ILU init test
2017-04-19 19:39:30.052 0:0:0>Begin: PIU TLU init test
2017-04-19 19:39:30.262 0:0:0>End : PIU TLU init test
2017-04-19 19:39:30.317 0:0:0>Begin: PIU PEU init test
2017-04-19 19:39:30.525 0:0:0>End : PIU PEU init test
2017-04-19 19:39:30.580 0:0:0>Begin: PIU intx interrupt test
2017-04-19 19:39:30.742 0:0:0>cpu_interrupt_handler, I/O interrupt.
2017-04-19 19:39:30.906 0:0:0>End : PIU intx interrupt test
2017-04-19 19:39:31.066 0:0:0>Begin: Probe PCI Devices
2017-04-19 19:39:40.908 0:0:0>PCIE PROBE devices found = 25
2017-04-19 19:39:41.120 0:0:0>End : Probe PCI Devices
2017-04-19 19:39:41.175 0:0:0>Begin: PIU PCI id test
2017-04-19 19:39:41.433 0:0:0>End : PIU PCI id test
2017-04-19 19:39:41.489 0:0:0>Begin: Network Tests
2017-04-19 19:39:41.652 0:0:0>Testing Network Device: NIU(s) [CMP0 ] ...
2017-04-19 19:39:41.863 0:0:0>Network Interface Unit Port 0 Tests ...
2017-04-19 19:39:59.120 0:0:0>Network Interface Unit Port 1 Tests ...
2017-04-19 19:40:16.430 0:0:0>Begin: XMAC Loopback - Port 0
2017-04-19 19:40:19.081 0:0:0>End : XMAC Loopback - Port 0
2017-04-19 19:40:19.136 0:0:0>Begin: XPCS Loopback - Port 0
2017-04-19 19:40:21.785 0:0:0>End : XPCS Loopback - Port 0
2017-04-19 19:40:21.840 0:0:0>Begin: SerDes Loopback - Port 0
2017-04-19 19:40:26.780 0:0:0>End : SerDes Loopback - Port 0
2017-04-19 19:40:26.835 0:0:0>Begin: XMAC Loopback - Port 1
2017-04-19 19:40:29.488 0:0:0>End : XMAC Loopback - Port 1
2017-04-19 19:40:29.545 0:0:0>Begin: XPCS Loopback - Port 1
2017-04-19 19:40:32.196 0:0:0>End : XPCS Loopback - Port 1
2017-04-19 19:40:32.250 0:0:0>Begin: SerDes Loopback - Port 1
2017-04-19 19:40:37.194 0:0:0>End : SerDes Loopback - Port 1
2017-04-19 19:40:37.355 0:0:0>End : Network Tests
2017-04-19 19:40:37.566 0:0:0>Functional CPU Tests.....
2017-04-19 19:40:37.725 0:0:0>Extended Memory Tests.....
2017-04-19 19:40:37.782 0:0:0>Begin: Print Mem Config
2017-04-19 19:40:37.788 0:0:0>Caches : Icache is ON, Dcache is ON.
2017-04-19 19:40:37.793 0:0:0> Total Memory = 00000000.00000000 ->
00000008.00000000
2017-04-19 19:40:37.800 0:0:0>End : Print Mem Config
2017-04-19 19:40:37.856 0:0:0>Begin: Block Mem Test
2017-04-19 19:40:38.003 0:0:0>Block Mem Test
00000000.10000000->00000008.00000000
2017-04-19 19:40:38.929 0:0:0>........
2017-04-19 19:42:10.642 0:0:0>Testing Gaps..
2017-04-19 19:42:10.697 0:0:0>........
2017-04-19 19:42:19.265 0:0:0>........
2017-04-19 19:42:27.726 0:0:0>........
2017-04-19 19:42:37.679 0:0:0>End : Block Mem Test
2017-04-19 19:42:37.766 0:0:0>INFO:
2017-04-19 19:42:37.819 0:0:0> POST Passed all devices.
2017-04-19 19:42:37.873 0:0:0>POST: Return to VBSC.
2017-04-19 19:42:37.927 0:0:0>Master set ACK for vbsc runpost command and
spin...
cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu
cpu cpu cpu cpu cpu cpu cpu
Device: niu
Device: pci-performance-counters
Device: ebus
/ebus@c0: serial
/pci@0: Device 0 pci
/pci@0/pci@0: Device 1 pci
/pci@0/pci@0/pci@1: Device 0 pci
/pci@0/pci@0/pci@1/pci@0: Device 1 pci
/pci@0/pci@0/pci@1/pci@0/pci@1: Device 0 pci
/pci@0/pci@0/pci@1/pci@0/pci@1/pci@0: Device 0 usb usb usb
/pci@0/pci@0/pci@1/pci@0: Device 2 pci
/pci@0/pci@0/pci@1/pci@0/pci@2: Device 0 network network
/pci@0/pci@0/pci@1/pci@0: Device 3 pci
/pci@0/pci@0/pci@1/pci@0/pci@3: Device 0 network network
/pci@0/pci@0: Device 2 pci
/pci@0/pci@0/pci@2: Device 0 scsi tape disk
/pci@0/pci@0: Device 8 pci
/pci@0/pci@0/pci@8: Device 0 pci
/pci@0/pci@0/pci@8/pci@0: Device 1 pci
/pci@0/pci@0/pci@8/pci@0/pci@1: Device 0 network network network network
/pci@0/pci@0/pci@8/pci@0: Device 2 pci
/pci@0/pci@0/pci@8/pci@0/pci@2: Device 0 Nothing there
/pci@0/pci@0/pci@8/pci@0: Device 8 pci
/pci@0/pci@0/pci@8/pci@0/pci@8: Device 0 Nothing there
/pci@0/pci@0/pci@8/pci@0: Device 9 pci
/pci@0/pci@0/pci@8/pci@0/pci@9: Device 0 fibre-channel fibre-channel
/pci@0/pci@0/pci@8/pci@0: Device a pci
/pci@0/pci@0/pci@8/pci@0/pci@a: Device 0 network network network network
/pci@0/pci@0: Device 9 pci
/pci@0/pci@0/pci@9: Device 0 fibre-channel fibre-channel
storage disk hub
SPARC Enterprise T5220, No Keyboard
Copyright (c) 1998, 2014, Oracle and/or its affiliates. All rights reserved.
OpenBoot 4.33.6.e, 32640 MB memory available, Serial #78404474.
Ethernet address 0:14:4f:ac:5b:7a, Host ID: 84ac5b7a.
Bad magic number in disk label
Can't open disk label package
ERROR: boot-read fail
Boot device: net File and args:
1000 Mbps full duplex Link up
Requesting Internet Address for 0:14:4f:ac:5b:7a
Requesting Internet Address for 0:14:4f:ac:5b:7a
Consoles: Open Firmware console
ERROR: Last Trap: Illegal Instruction
{0} ok boot net bsd.rd
cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu
cpu cpu cpu cpu cpu cpu cpu
Device: niu
Device: pci-performance-counters
Device: ebus
/ebus@c0: serial
/pci@0: Device 0 pci
/pci@0/pci@0: Device 1 pci
/pci@0/pci@0/pci@1: Device 0 pci
/pci@0/pci@0/pci@1/pci@0: Device 1 pci
/pci@0/pci@0/pci@1/pci@0/pci@1: Device 0 pci
/pci@0/pci@0/pci@1/pci@0/pci@1/pci@0: Device 0 usb usb usb
/pci@0/pci@0/pci@1/pci@0: Device 2 pci
/pci@0/pci@0/pci@1/pci@0/pci@2: Device 0 network network
/pci@0/pci@0/pci@1/pci@0: Device 3 pci
/pci@0/pci@0/pci@1/pci@0/pci@3: Device 0 network network
/pci@0/pci@0: Device 2 pci
/pci@0/pci@0/pci@2: Device 0 scsi tape disk
/pci@0/pci@0: Device 8 pci
/pci@0/pci@0/pci@8: Device 0 pci
/pci@0/pci@0/pci@8/pci@0: Device 1 pci
/pci@0/pci@0/pci@8/pci@0/pci@1: Device 0 network network network network
/pci@0/pci@0/pci@8/pci@0: Device 2 pci
/pci@0/pci@0/pci@8/pci@0/pci@2: Device 0 Nothing there
/pci@0/pci@0/pci@8/pci@0: Device 8 pci
/pci@0/pci@0/pci@8/pci@0/pci@8: Device 0 Nothing there
/pci@0/pci@0/pci@8/pci@0: Device 9 pci
/pci@0/pci@0/pci@8/pci@0/pci@9: Device 0 fibre-channel fibre-channel
/pci@0/pci@0/pci@8/pci@0: Device a pci
/pci@0/pci@0/pci@8/pci@0/pci@a: Device 0 network network network network
/pci@0/pci@0: Device 9 pci
/pci@0/pci@0/pci@9: Device 0 fibre-channel fibre-channel
storage disk hub
SPARC Enterprise T5220, No Keyboard
Copyright (c) 1998, 2014, Oracle and/or its affiliates. All rights reserved.
OpenBoot 4.33.6.e, 32640 MB memory available, Serial #78404474.
Ethernet address 0:14:4f:ac:5b:7a, Host ID: 84ac5b7a.
Boot device: /pci@0/pci@0/pci@1/pci@0/pci@2/network@0 File and args: bsd.rd
1000 Mbps full duplex Link up
Requesting Internet Address for 0:14:4f:ac:5b:7a
Requesting Internet Address for 0:14:4f:ac:5b:7a
Requesting Internet Address for 0:14:4f:ac:5b:7a
Link is down. Restarting network initialization
1000 Mbps full duplex Link up
Requesting Internet Address for 0:14:4f:ac:5b:7a
Consoles: Open Firmware console
ERROR: Last Trap: Illegal Instruction
{0} ok ok boot net bsd.md
cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu cpu
cpu cpu cpu cpu cpu cpu cpu
Device: niu
Device: pci-performance-counters
Device: ebus
/ebus@c0: serial
/pci@0: Device 0 pci
/pci@0/pci@0: Device 1 pci
/pci@0/pci@0/pci@1: Device 0 pci
/pci@0/pci@0/pci@1/pci@0: Device 1 pci
/pci@0/pci@0/pci@1/pci@0/pci@1: Device 0 pci
/pci@0/pci@0/pci@1/pci@0/pci@1/pci@0: Device 0 usb usb usb
/pci@0/pci@0/pci@1/pci@0: Device 2 pci
/pci@0/pci@0/pci@1/pci@0/pci@2: Device 0 network network
/pci@0/pci@0/pci@1/pci@0: Device 3 pci
/pci@0/pci@0/pci@1/pci@0/pci@3: Device 0 network network
/pci@0/pci@0: Device 2 pci
/pci@0/pci@0/pci@2: Device 0 scsi tape disk
/pci@0/pci@0: Device 8 pci
/pci@0/pci@0/pci@8: Device 0 pci
/pci@0/pci@0/pci@8/pci@0: Device 1 pci
/pci@0/pci@0/pci@8/pci@0/pci@1: Device 0 network network network network
/pci@0/pci@0/pci@8/pci@0: Device 2 pci
/pci@0/pci@0/pci@8/pci@0/pci@2: Device 0 Nothing there
/pci@0/pci@0/pci@8/pci@0: Device 8 pci
/pci@0/pci@0/pci@8/pci@0/pci@8: Device 0 Nothing there
/pci@0/pci@0/pci@8/pci@0: Device 9 pci
/pci@0/pci@0/pci@8/pci@0/pci@9: Device 0 fibre-channel fibre-channel
/pci@0/pci@0/pci@8/pci@0: Device a pci
/pci@0/pci@0/pci@8/pci@0/pci@a: Device 0 network network network network
/pci@0/pci@0: Device 9 pci
/pci@0/pci@0/pci@9: Device 0 fibre-channel fibre-channel
storage disk hub
SPARC Enterprise T5220, No Keyboard
Copyright (c) 1998, 2014, Oracle and/or its affiliates. All rights reserved.
OpenBoot 4.33.6.e, 32640 MB memory available, Serial #78404474.
Ethernet address 0:14:4f:ac:5b:7a, Host ID: 84ac5b7a.
Boot device: /pci@0/pci@0/pci@1/pci@0/pci@2/network@0 File and args: bsd.md
1000 Mbps full duplex Link up
Requesting Internet Address for 0:14:4f:ac:5b:7a
Requesting Internet Address for 0:14:4f:ac:5b:7a
Consoles: Open Firmware console
ERROR: Last Trap: Illegal Instruction
{0} ok
Thoughts? What have I done wrong?
Thanks,
Michelle
