On Wed, Jul 18, 2007 at 10:27:17AM -0700, David Brownell wrote:
> On Wednesday 18 July 2007, Pierre Ossman wrote:
> > On Tue, 17 Jul 2007 09:11:15 -0700
> > David Brownell <[EMAIL PROTECTED]> wrote:
> > 
> > > Ideally, someone with access to full MMC and SD specs can see
> > > what they say about the SPI clocking.  The simplified SD specs
> > > omit the timing diagrams.
> > >  
> > 
> > I can probably help out there.
> > 
> > According to the specs, both mode 0 and mode 3 are valid. The idle
> > polarity simply isn't specified, only that data shall be sampled on
> > rising edge. Hence mode 0 or 3.
> 
> Thanks.  In that case, I'm thinking there *IS* a bug of some kind
> in the controller driver Anton is using, else mode 3 would work
> for him like it (evidently) works for everyone else.

I've checked with MPC8323E reference manual, and according to it
spi_mpc83xx is doing right thing.

> I'll see about making time to see if mode 0 works for me too; but
> even if it does, I'd prefer to leave the driver the way it is now
> instead of changing it to cover up for that mpc83xx bug ... plus,
> I just like CPHA=1 modes better because they don't need to start
> with that strange half-clock.  ;)

Well. As Pierre Ossman told, it should work at any mode. That also
proves that it's not mpc83xx's bug (because even if it would be a
bug, and spi_mpc83xx having inversed values, it's still should work).

So, it's likely depends on spi controller, maybe some timing issues
or signal shapes, which distracts SD/MMC... Not sure.

But then, may I ask for "alt_mode" (bool) platform data variable?

Thanks!

-- 
Anton Vorontsov
email: [EMAIL PROTECTED]
backup email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2

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