Hi,
it seems to me that the spi_sh_msiof.c driver configures REDG and TEDG wrongly.
TEDG==0 outputs data at the **rising edge** of the clock and REDG==0 samples
data at the **falling edge** of the clock. Therefore for SPI, TEDG must be
equal to REDG, otherwise the last byte received is not sampled in the SPI mode 3
The SH7723 HW Reference Manual explains the setting in Figure 20.20 and Figure
20.21 ("SPI Clock and data timing")
Signed-off-by: Markus Pietrek <[email protected]>
Acked-by: Magnus Damm <[email protected]>
---
drivers/spi/spi_sh_msiof.c | 14 ++++++--------
1 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi_sh_msiof.c b/drivers/spi/spi_sh_msiof.c
index 51e5e1d..af15e97 100644
--- a/drivers/spi/spi_sh_msiof.c
+++ b/drivers/spi/spi_sh_msiof.c
@@ -173,13 +173,11 @@ static void sh_msiof_spi_set_pin_regs(struct
sh_msiof_spi_priv *p,
int edge;
/*
- * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG(!)
- * 0 0 10 10 1 0
- * 0 1 10 10 0 1
- * 1 0 11 11 0 1
- * 1 1 11 11 1 0
- *
- * (!) Note: REDG is inverted recommended data sheet setting
+ * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
+ * 0 0 10 10 1 1
+ * 0 1 10 10 0 0
+ * 1 0 11 11 0 0
+ * 1 1 11 11 1 1
*/
sh_msiof_write(p, FCTR, 0);
@@ -193,7 +191,7 @@ static void sh_msiof_spi_set_pin_regs(struct
sh_msiof_spi_priv *p,
edge = cpol ? cpha : !cpha;
tmp |= edge << 27; /* TEDG */
- tmp |= !edge << 26; /* REDG */
+ tmp |= edge << 26; /* REDG */
tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */
sh_msiof_write(p, CTR, tmp);
}
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