On Fri, Jan 29, 2010 at 6:37 AM, Pietrek, Markus <[email protected]> wrote: > Hi, > > it seems to me that the spi_sh_msiof.c driver configures REDG and TEDG > wrongly. TEDG==0 outputs data at the **rising edge** of the clock and REDG==0 > samples data at the **falling edge** of the clock. Therefore for SPI, TEDG > must be equal to REDG, otherwise the last byte received is not sampled in the > SPI mode 3 > > The SH7723 HW Reference Manual explains the setting in Figure 20.20 and > Figure 20.21 ("SPI Clock and data timing") > > > Signed-off-by: Markus Pietrek <[email protected]> > Acked-by: Magnus Damm <[email protected]>
Patch is whitespace damaged and so doesn't cleanly apply. It's been picked up anyway since this one is pretty trivial, but you should look into fixing your mailer for sending patches. Thanks, g. ------------------------------------------------------------------------------ The Planet: dedicated and managed hosting, cloud storage, colocation Stay online with enterprise data centers and the best network in the business Choose flexible plans and management services without long-term contracts Personal 24x7 support from experience hosting pros just a phone call away. http://p.sf.net/sfu/theplanet-com _______________________________________________ spi-devel-general mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/spi-devel-general
