On 4/25/10, H Hartley Sweeten <hartl...@visionengravers.com> wrote:
> > - /* clear the interrupt */
> > - ep93xx_spi_write_u8(espi, SSPICR, 0);
> >
> > /*
> > * If we got ROR (receive overrun) interrupt we know that
> something is
> > * wrong. Just abort the message.
> > */
> > if (unlikely(irq_status & SSPIIR_RORIS)) {
> > + /* clear the overrun interrupt */
> > + ep93xx_spi_write_u8(espi, SSPICR, 0);
> > dev_warn(&espi->pdev->dev,
> > "receive overrun, aborting the message\n");
> > espi->current_msg->status = -EIO;
> > } else {
>
> With this patch the interrupts only get cleared if it's a ROR interrupt.
>
> Do the RIS/TIS interrupts get cleared by the upper layers? If so, do we
> really need to clear the ROR interrupt here?
RX/TX interrupts are cleared by emptying the RX FIFO or filling the TX
FIFO to less/more than half full. There is no explicit clearing of the
IRQ.
The ROR interrupt instead remains active until you explicitly clear it
by writing (anything( to SSPICR, so it would remain on forever
otherwise.
M
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