On 15 November 2012 00:17, Mark Brown <[email protected]> wrote: > On Wed, Nov 14, 2012 at 11:22:26PM +0100, Jonas Gorski wrote: >> The BCM63XX SPI controller does not support keeping CS asserted after >> sending its buffer. This breaks common usages like spi_write_then_read, >> where it is expected to be kept active during the whole transfers. > >> Work around this by combining the transfers into one if the buffer >> allows. For spi_write_then_read, use the prepend byte feature to write >> to "prepend" the write if it is less than 15 bytes, allowing the whole >> fifo size for the read. > > This is only going to work around a relatively small subset of cases so > it doesn't seem worth rushing in. The normal fix for such issues is to > control /CS as a GPIO.
Well, one of the "small" subsets is SPI attached flash, those need write then read or write then write with CS asserted for most operations, too. And I'm not sure if controlling CS as a GPIO is an option on bcm63xx, at least not for the CS's commonly used (the others have GPIO overlays on some chips). OTOH booting from SPI flash isn't properly supported yet anyway in vanilla linux for bcm63xx. Jonas ------------------------------------------------------------------------------ Monitor your physical, virtual and cloud infrastructure from a single web console. Get in-depth insight into apps, servers, databases, vmware, SAP, cloud infrastructure, etc. Download 30-day Free Trial. Pricing starts from $795 for 25 servers or applications! http://p.sf.net/sfu/zoho_dev2dev_nov _______________________________________________ spi-devel-general mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/spi-devel-general
