On Tue, Dec 18, 2012 at 01:47:40PM +0800, chao bi wrote: > Dear Linus, > Thanks for your kind comments. Seems you were viewing the 1st version, I've > submitted 2nd version and to deliver the 3rd version soon, will include you > for review. Was the third version posted?
Also I have some questions on this approach. Is this driver for SSP ip or SPI ip, looks like latter. In both the cases there are some existing drivers in kernel and adding one more IMHO doesnt make sense. What we really need a common core for dw IP and SSP IP (i think pxa uses same stuff). That way lot of code will get reduced from driver > > > > > +#define SRAM_BASE_ADDR 0xfffdc000 > > > > Should be passed as resource, se above reasoning for the > > "I2C" base address. What happens on next ASIC spin when > > the engineer move this base offset etc, don't you have any > > system discovery? > This is fix value for Moorestown & Medfield platforms as what is > declared in the file header. If any hardware change, the address should > be changed accordantly. Why do you wnat to change this latter, pls add it as a resouce or since this is a PCI device you can use PCI table driver data. Also why would SSP care about SRAM, I am not sure I follow it?? Lastly if you have dedicated SRAM for your use, it should be in PCI BAR and not hard coded like this!! -- ~Vinod ------------------------------------------------------------------------------ Master Java SE, Java EE, Eclipse, Spring, Hibernate, JavaScript, jQuery and much more. Keep your Java skills current with LearnJavaNow - 200+ hours of step-by-step video tutorials by Java experts. SALE $49.99 this month only -- learn more at: http://p.sf.net/sfu/learnmore_122612 _______________________________________________ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
