Hi Tom,
Robert,
>
> Right, but isn't that precisely one of the arguments that 16 byte SIDs are
> a problem? For instance, if my parsing buffer is 128 bytes then that allows
> an SRH with at most four or maybe five SIDs if I'm not mistaken. It seems
> like the smaller SID size of SRV6+, even with the DOH PSSI, option still
> would produce smaller a header chain than SRV6 and thereby allow more
> segments in the header.
>
Let me just send a ref to one of the IETF emails from eng of one of the
major NPU data plane vendor ...
He said:
It clearly depends on the device capabilities. For a device with a
parsing buffer of *256 bytes*
that should be plenty of room for HBH options, SR header,
transport layer, etc.
https://mailarchive.ietf.org/arch/msg/ippm/RapEwM8JcMZjFZtqcsF1NqXWDUI#
I also know from other direct discussions that 256 bytes is the defacto
standard in modern chips.
But the reality is and this has been already said as well that most use
cases use just a few SIDs say anywhere from 1-4. Beyond that while of
course you will find customer stating I need 10 you can use uSID or
draft-li-spring-compressed-srv6-np
Thx,
R.
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