What are the limiting factors for the bus speed on the S900? As we mentioned before, the XLR8 CarrierZIF board has a setting that will "request" 66MHz bus from the machine, so that and the variable bus speed implies a PLL clock. Is it just that the PLL in the S900 isn't up to generating that signal, or are there other components in the system that limit speed?
There is no CPU bus clock, nor PLL on the S900 board, nor on any of the x500, x600 Apple machines (known collectively as the PowerSurge family). All clock signals for the CPU bus are supplied from the CPU slot. Pins 9 through 14 of the CPU connector carry clock signals (identical, in phase, signals) from the CPU slot to the components on the motherboard which need a CPU bus clock. These include the Hammerhead memory control/bus arbiter, the Bandit CPU/PCI bridge and possibly the two Data Path controllers.
I do not have a Carrier card. However, I do have an example ZIF CPU module here and see that there is no clock on board. Therefore, I assume that the Carrier card supplies the bus clock to the ZIF CPU module and to the motherboard. So the bus clock setting should be the on the ZIF Carrier Card.
The PowerLogix ZIF has adjustments on board for the bus multiplier (thanks to Will S for that info). So, unless my trail of deduction is incorrect ( :-) ) one adjusts the CPU bus clock speed on the ZIF Carrier card and the CPU bus multiplier on the ZIF card itself.
On another note, how is the PCI bus clock derived on the S900?
There's a 33.3333 MHz oscillator nailed to the motherboard. It passes through a clock buffer and the divided/amplified signal is distributed to the PCI slots, Bandit chip, PCI bus arbiter, PCI-PCI Bridge chip and the Grand Central IO chip (Grand Central is a PCI device).
Jeff Walther
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